Cobham Gaisler AB provides IP cores and supporting development tools for embedded processors based on the SPARC architecture. We specialize in digital hardware design for both commercial and aerospace applications

GRETH_GBIT 10/100/1000 Ethernet MAC

The GRETH_GBIT core implements a 10/100/1000 Mbit/s Ethernet Media Access Controller (MAC) with AMBA host interface. The core implements the 802.3-2002 Ethernet standard. Receive and transmit data is autonomously transferred between the Ethernet MAC and the AMBA AHB bus using DMA transfers. Through the use of receive and transmit descriptors, multiple ethernet packets can be received and transmitted without CPU involvement. The GRETH_GBIT provides support for the MII and GMII PHY interfaces. Hardware support is also provided for the EDCL UDP debugging protocol. For critical space applications, a fault-tolerant version of GRETH_GBIT is available with full SEU protection of all RAM blocks.

GRETH block diagram


  • AMBA AHB back end with DMA
  • Support for Scatter/Gather DMA
  • Checksum offloading in hardware for TCP/IP/UDP for both receiver and transmitter
  • Descriptor based autonomous multi-packet transfer
  • Portable


  • VHDL source code or FPGA/ASIC netlist
  • Stand-alone testbench
  • Optional plug and play interface for GRLIB IP-library
  • User's manual
  • Driver for RTEMS, eCos, Linux 2.0, Linux 2.6 and VxWorks.

Area and timing

The GRETH_GBIT is inherently portable and can be implemented on most FPGA and ASIC technologies. The table below shows the approximate area and frequency for two different GRETH_GBIT configurations on Altera Stratix, Xilinx Virtex2 and ASIC technologies.

(LUTs / RAM / Frequency) Virtex2
(ALMs / M512 / M4K / Frequency) Altera

Configuration Stratix Virtex2 ASIC gates
GRETH_GBIT 2,300 / 1 / 9 / 130 5,000 / 2 / 90 26,000
GRETH_GBIT + EDCL 2,800 / 1 / 11 / 130  6,100 / 4 / 90 32,000

The GRETH_GBIT core can be licensed commercially, either stand-alone or as part of the GRLIB IP library. It is delivered either as VHDL source-code or as a netlist. Evaluation netlists can also be delivered for most technologies.


The EDCL is an optional hardware unit providing read/write access to the AHB bus through Ethernet using an UDP based protocol. It operates in parallel with the MAC DMA and does not interfere with the  normal network traffic other than lowering performance. Speeds up to 500 Mbit/s effective throughput have been achieved when accessing the AHB bus through the EDCL using the GRMON debug monitor.

Speed with TCP/IP software stacks

Although the theoretical maximum speed is near 1 Gbit/s for a gigabit network this is never reached in practice. When using software TCP/IP stacks from the supported operating systems the limiting factor will be the processing power of the CPU. The tables below show the speed that can typically be achieved with different CPU configurations using Linux 2.6 which has the most extensive support for the offloading features in the GRETH_GBIT. The other operating systems will usually be slower since they lack support for one or more of these features. The speed measurements were done with the Test TCP (TTCP) utility which is a benchmarking tool for measuring TCP and UDP performance. The Tx and Rx columns in the tables refer to the speed achieved when transmitting and receiving with TTCP respectively. All the tests were run in TCP mode. 

Spartan 3 100 Mbit network

 Freq I-cache   D-cache
 Tx Rx
40 MHz 1 * 1 k 1 * 1 k  15 Mbit/s 21 Mbit/s
40 MHz 1 * 16 k 1 * 16 k  24 Mbit/s 30 Mbit/s
45 MHz 1 * 16 k 1 * 16 k  27 Mbit/s 34 Mbit/s
46 MHz  1 * 32 k 1 * 8 k  30 Mbit/s 37 Mbit/s

Virtex 4 1000 Mbit network

 Freq  I-cache D-cache  Tx Rx
 70 MHz  1 * 32 k  1 * 16 k  41 Mbit/s 45 Mbit/s

Virtex 5 1000 Mbit network

 Freq  I-cache D-cache Tx Rx
 85 MHz  2 * 8 k  1 * 8 k  40 Mbit/s  55 Mbit/s
 85 MHz  4 * 8 k  4 * 4 k  62 Mbit/s  67 Mbit/s