The GR1553B core implements the MIL-STD-1553B (Notice 2) data bus protocol, with ability to serve as Bus Controller (BC), Remote Terminal (RT) or Bus Monitor (BM).
The core is connected to the MIL-STD-1553B bus via a dual transceiver interface (txP/N/en, rxP/N/en). On the system side, the core connects to the AMBA bus as an AHB master for DMA transfers and an APB slave for register access. The core uses a separate 20 MHz clock for the MIL-STD-1553B codec, and runs at any AMBA clock frequency from 10 MHz and upwards.
As Bus Controller, the core works using an automated transfer list concept. The BC supports all permitted transfer types and includes other features such as automatic retries on same or alternating buses, extended RT response timeout for systems with bus repeaters, transfer list looping and branches.
In Remote Terminal mode, the core uses a subaddress table where the user can specify per subaddress whether to accept transmit, receive or broadcast transfers, and maximum transfer size. For storing transfer results and data, linked lists of descriptors are used, with each descriptor pointing to a data
The Bus Monitor can be run by itself or simultaneously while the core is running as RT or BC. It listens to traffic on the bus and logs the words in a ring buffer. The BM can filter traffic to get only the RT address, subaddress or mode codes of interest, and also log parity and Manchester code errors. All entries in the bus monitor log are time stamped.
Development boards for early development and fast prototyping of systems using the GR1553B core are available, equipped with either Xilinx or Actel FPGA. Each board can be operated either stand-alone or installed as a compact PCI plug-in card.