Cobham Gaisler AB provides IP cores and supporting development tools for embedded processors based on the SPARC architecture. We specialize in digital hardware design for both commercial and aerospace applications

GRSPW SpaceWire Link

The GRSPW core implements a SpaceWire link controller with RMAP support and AMBA host interface. The core complies to the SpaceWire standard (ECSS-E-ST-50-12C) with the protocol identification extension (ECSS-E- ST-50-51C ) and RMAP protocol (ECSS-E-ST-50-52C). Receive and transmit data is autonomously transferred between the SpaceWire Codec and the AMBA AHB bus using DMA transfers. Through the use of receive and transmit descriptors, multiple SpaceWire packets can be received and transmitted without CPU involvement. The GRSPW control registers are accessed through an APB interface. For critical space applications, a fault-tolerant (FT) version of GRSPW is available with full SEU protection of all RAM blocks.

GRSPW block diagram

The GRSPW is inherently portable and can be implemented on most FPGA and ASIC technologies. The table below shows the approximate Cell/LUT count and frequency for seven different GRSPW configurations on Actel RTAX, Xilinx Spartan3, Xilinx Virtex2 and ASIC technologies. Please note that these numbers are only typical values. Some of them might  vary  as much as 25% in specific implementations.

(Cells / RAM blocks / AHB MHz / SPW MHz)

Core configuration RTAX Spartan3 Virtex2 ASIC
GRSPW 3,000 / 3 / 40 / 100  1,900 / 3 / 65 / 180 1,900 / 3 / 80 / 200 10,000 gates
GRSPW + RMAP 4,400 / 4 / 40 / 100  3,300 / 4 / 60 / 180 3,400 / 4 / 80 / 200 18,000 gates
GRSPW + 2P 3,300 / 3 / 40 / 100  2,000 / 3 / 60 / 180 2,000 / 3 / 80 / 200 11,000 gates
GRSPW + RMAP + 2P  4,700 / 4 / 40 / 100   3,400 / 4 / 60 / 180 3,500 / 4 / 80 / 200 18,000 gates
GRSPW-FT 3,100 / 5 / 40 / 100  2,000 / 5 / 65 / 180 2,000 / 5 / 80 / 200 11,000 gates
GRSPW-FT + RMAP 4,400 / 6 / 40 / 100  3,400 / 6 / 60 / 180 3,500 / 6 / 80 / 200 18,000 gates
GRSPW-FT + RMAP + 2P 4,700 / 6 / 40 / 100  3,500 / 6 / 60 / 180 3,500 / 6 / 80 / 200 18,000 gates

Features

  • Full implementation of SpaceWire standard
  • Protocol ID extension ECSS-E-50-11
  • Optional RMAP protocol ECSS-E-50-11
  • AMBA AHB back-end with DMA
  • Descriptor-based autonomous multi-packet transfer
  • Low area and high frequency
  • SEU protection fault-tolerance
  • Portable

Benefits

  • Tested and verified against several other SpaceWire cores
  • Low area and high frequency
  • Easily portable between FPGA and ASIC
  • Low-cost project license
  • SEU protection of all RAM blocks

Deliverables

  • FPGA/ASIC netlist
  • Stand-alone testbench
  • Optional plug and play interface for GRLIB IP library
  • User's manual
  • Driver for RTEMS and VxWorks