Cobham Gaisler AB provides IP cores and supporting development tools for embedded processors based on the SPARC architecture. We specialize in digital hardware design for both commercial and aerospace applications

USB 2.0 Host Controller

grusbhc-hostThe USB 2.0 Host Controller provides a link between the AMBA on-chip bus and the Universal Serial Bus (USB). The host controller supports High-, Full- and Low-Speed USB traffic.

USB 2.0 High-Speed functionality is supplied by an enhanced host controller implementing the Enhanced Host Controller Interface (EHCI). Full- and Low-Speed functionality (USB 2.0 and USB 1.1) is supplied by one or more companion controllers implementing the Universal Host Controller Interface (UHCI). The Port Router supplies the dynamic connection between the host controllers and the USB transceivers. The figure below shows a typical USB 2.0 host system with an enhanced host controller and a companion controller.

The core can handle up to 15 downstream ports, where each port can handle all three USB speeds. Port routing within the core is highly configurable. The designer has choices ranging from handling Full/Low-Speed traffic with one companion controller per port, to having one companion controller handle all ports. The modularity of the core enables the designer to configure High- or Full/Low-Speed only products. Both controller types have support for big and little endian systems, with the option to adjust the register interfaces' byte order to fit the target platform.

The enhanced host controller has support for Asynchronous Park Mode to allow consecutive bulk transactions to the same endpoint and a NAK counter to limit unnecessary memory accesses. The universal host controller's interface has been extended to report over current conditions. The core supports UTMI+ 16-bit transceivers at 30 MHz and 8-bit transceivers at 60 MHz, and ULPI 8-bit transceivers at 60 MHz.

grusbhc-block

The host controller core is inherently portable and can be implemented on most FPGA and ASIC technologies. Both area and timing of the core depends strongly on the selected configuration, target technology and the used synthesis tool.

Size and performance

Core configuration # Ports Xilinx Virtex 4*    
(Cells / RAM / MHz)
ASIC
Gates
Universal host controller
(USB Full - and Low-Speed traffic only) 1 3000 / 1 / 80 MHz 25000
 
Enhanced host controller
(USB High-Speed traffic only) 1 9000 / 3 / 80 MHz 70000
 
Enhanced host controller with one universal companion  
controller** (supports all USB traffic speeds) 1 12000 / 3 / 80 MHz 95000
  2 13000 / 4 / 80 MHz 105000
  4 15000 / 4 / 80 MHz 125000
  8 20000 / 4 / 80 MHz 155000
  12 24000 / 4 / 80 MHz 195000
  15 27000 / 4 / 80 MHz 215000

* (LUTs / RAM blocks / AHB system clock MHz)

** The single companion controller handles all ports. The core can also be configured to include multiple companion controllers.