Cobham Gaisler AB provides IP cores and supporting development tools for embedded processors based on the SPARC architecture. We specialize in digital hardware design for both commercial and aerospace applications

USB Debug Communication Link (USBDCL)

USB DCL block diag 1 The Universal Serial Bus Debug Communication Link (USBDCL) provides an interface between an USB 2.0 bus and an AMBA-AHB bus. An external PHY compliant with either UTMI, UTMI+ or ULPI is needed to connect to the USB. The USBDCL is an AHB master and provides read and write access to the whole AHB address space using a simple protocol over two USB bulk endpoints. The figure below shows how the USBDCL should be connected to the PHY. The USBDCL is a function implementation that utilizes the GRUSBDC device controller for the USB interface.


Protocol

The USBDCL protocol uses one IN and one OUT bulk endpoint (in addition to the mandatory control endpoint). Read and write commands to the AHB bus and write data are sent to the OUT endpoint. Read data is returned on the IN endpoint. The protocol is supported in the GRMON debug tool using libusb and provides maximum speeds of up to 30 MBit/s to the AHB bus over an USB 2.0 bus. The protocol specification is freely available so it is possible to develop own applications that utilize the USBDCL. Fore more information please see the USBDCL section in the grip manual.

USBDCL block diagram 2

Area

The USBDCL uses approximately 2000 LUTs and 8 blockrams on the Xilinx Spartan 3 technology. The maximum frequency is 80 MHz.

Availability

The USBDCL is available under a commercial license.