GRSIM LEON MP Simulator
Introduction
GRSIM is a simulation framework for SOC devices based on the AMBA AHB bus. The simulator consists of a AHB bus model with underlying event-driven simulation engine. C-models of IP cores are attached to the AHB model, and linked into a final simulator. The GRSIM simulator includes pre-compiled simulation models of the IP cores in the GRLIB IP library, including the LEON3 processor. Models of LEON2 and its on-chip peripherals are also available for simulation of legacy systems. The GRSIM library is re-entrant and thread-safe, and allows simulation of any number of buses and IP cores. It is therefore particularly suitable for simulating multi-processor LEON3 systems.
- Emulation of multiple LEON2 and LEON3 processors
- Simulation models for GRLIB IP cores
- Standalone operation and remote connection to GNU debugger (gdb)
- 64-bit time for unlimited simulation periods
- Unlimited number of user-defined IP models
- Instruction trace buffer
- Stack backtrace with symbolic information
- Unlimited number of beakpoints and watchpoints
- Re-entrant and thread-safe library
Usage
GRSIM can be run in stand-alone mode, or connected through a network socket to the GNU gdb debugger. In stand-alone mode, a variety of debugging commands are available to allow manipulation of memory contents and registers, breakpoint/watchpoint insertion and performance measurement. Connected to gdb, GRSIM acts as a remote target and supports all gdb debug requests. The communication between gdb and TSIM is performed using the gdb extended-remote protocol. Any third-party debugger supporting this protocol can be used.
Timing
The simulator is cycle true, i.e a simulator time is maintained and incremented according the instruction timing of processors and cores. The time resolution is 1 AHB clock. The simulator time is maintained using 64-bit values providing virtually unlimited simulation time. The transfers on the AHB bus are transaction-based for maximum performance.
LEON2/3 emulation
Simulation models of LEON2 and LEON3 processor cores are provided pre-compiled with the simulator. The models are parametrizable and can emulate most processor configurations. The LEON3 model also emulates the behaviour of the MMU.
Custom IP core emulation
A custom simulation model of an IP core is typically written in C, and linked together with the GRSIM library. The custom simulation model has access to the simulator event queue, interrupts and other internal data structures, allowing for accurate and timing true emulation. This provides high simulation performance and capability to communicate with simulator frameworks such as EUROSIM, SIMSAT or System-C.
Performance
GRSIM is highly optimised for speed and provides simulation performance of more than 5 MIPS on a high-end PC. GRSIM can also accelerate simulation time when the emulated application is in idle mode. A collection of performance meassures are automatically calculated and can be displayed with the 'perf' command:
