Cobham Gaisler AB provides IP cores and supporting development tools for embedded processors based on the SPARC architecture. We specialize in digital hardware design for both commercial and aerospace applications



GRSIM is a simulation framework for SOC devices based on the AMBA AHB bus. The simulator consists of a AHB bus model with underlying event-driven simulation engine. C-models of IP cores are attached to the AHB model, and linked into a final simulator. The GRSIM simulator includes pre-compiled simulation models of the IP cores in the GRLIB IP library, including the LEON3 and LEON4 processors. Models of LEON2 and its on-chip peripherals are also available for simulation of legacy systems. The GRSIM library is re-entrant and thread-safe, and allows simulation of any number of buses and IP cores. It is therefore particularly suitable for simulating multi-processor LEON3 and LEON4 systems.

  • Emulation of LEON2 and multiple LEON3 and LEON4 processors
  • Simulation models for GRLIB IP cores
  • Standalone operation and remote connection to GNU debugger (gdb)
  • 64-bit time for unlimited simulation periods
  • Unlimited number of user-defined IP models of AHB slaves and APB slaves
  • Instruction trace buffer
  • Stack backtrace with symbolic information
  • Re-entrant and thread-safe library


GRSIM can be run in stand-alone mode, or connected through a network socket to the GNU gdb debugger. In stand-alone mode, a variety of debugging commands are available to allow manipulation of memory contents and registers, breakpoint/watchpoint insertion and performance measurement. Connected to gdb, GRSIM acts as a remote target and supports all gdb debug requests. The communication between gdb and GRSIM is performed using the gdb extended-remote protocol. Any third-party debugger supporting this protocol can be used.


The simulator time is maintained and incremented according the instruction timing of processors and cores. The time resolution is 1 AHB clock. The simulator time is maintained using 64-bit values providing virtually unlimited simulation time. The transfers on the AHB bus are transaction-based for maximum performance.

LEON2/3/4 emulation

Simulation models of LEON2, LEON3 and LEON4 processor cores are provided pre-compiled with the simulator. The models are parametrizable and can emulate most processor configurations. The LEON3/LEON4 models also emulates the behaviour of the MMU.

Custom IP core emulation

A custom simulation model of an IP core is typically written in C, and linked together with the GRSIM library. The custom simulation model has access to the simulator event queue, interrupts and other internal data structures, allowing for accurate emulation. This provides high simulation performance and capability to communicate with any other framework (e.g. such as EUROSIM or SIMSAT).


GRSIM is highly optimised for speed and provides simulation performance of more than 5 MIPS on a high-end PC. A collection of performance measures are automatically calculated and can be displayed with the 'perf' command:


To download GRSIM or the user's manual, please proceed to the download page.