Cobham Gaisler AB provides IP cores and supporting development tools for embedded processors based on the SPARC architecture. We specialize in digital hardware design for both commercial and aerospace applications

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Exploring Register File and Memory Organization in ASIP Synthesis Written by Sandi Habinc 8353
Comparison of the Performance of Microprocessors for Space-based Navigation Applications 9161
Successful Use of an Open Source Processor in a Commercial ASIC 8318
Experiences Designing a System-on-a-Chip for Small Satellite Data Processing and Control Written by Administrator 8995
A Pipelined SoPC Architecture for 2.5 Gbps Network Processing Written by Administrator 7871
Safety-Critical Architectures for Automotive Applications Written by Administrator 7800
Hardware/Software Co-testing of Embedded Memories in Complex SOCs Written by Administrator 8090
Analysis of SEU effects in a pipelined processor Written by Administrator 9531
Low power error resilient encoding for on-chip data buses Written by Administrator 7868
Design Flow for HW / SW Acceleration Transparency in the ThumbPod Secure Embedded System Written by Administrator 10572
Development cost and size estimation starting from high-level specifications Written by Administrator 9650
Reconfigurable Hardware in Wearable Computing Nodes Written by Administrator 7950
Hardware/Software Co-Training Written by Administrator 8134
An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Written by Administrator 8080
Mixed Static/Dynamic Profiling for Dictionary Based Code Compression Written by Administrator 7868
Embedded 32-Bit RISC IP Cores and OPEX JavaBytecode Folding Written by Administrator 7835
Architecture, Memory and Interface Technology Integration of an Industrial/Academic Configurable SoC Written by Administrator 9130
Liquid Architecture Written by Administrator 7783