Cobham Gaisler AB provides IP cores and supporting development tools for embedded processors based on the SPARC architecture. We specialize in digital hardware design for both commercial and aerospace applications

SPI to AHB Bridge

The SPI to AHB bridge is an SPI slave that provides a link between a SPI bus (that consists of two data signals, one clock signal and one select signal) and AMBA AHB. On the SPI bus the slave acts as an SPI memory device where accesses to the slave are translated to AMBA accesses. The core can translate SPI accesses to AMBA byte, half-word or word accesses. The access size to use is configurable via the SPI bus.

The core synchronizes the incoming clock and can operate in systems where other SPI devices are driven by asynchronous clocks.

Features

  • Provides bridge between SPI (slave) and AMBA AHB (master)
  • Optional AMBA APB interface
  • SPI mode selected at implementation time
  • AMBA access size is dynamically programmable
  • Instruction set similar to common SPI Flash memory devices
  • Optional protection is specified memory area(s)

For more information, please see the GRLIB IP Core User's Manual

Availability

The core is available under a commercial license and also under the GPL.