Cobham Gaisler AB provides IP cores and supporting development tools for embedded processors based on the SPARC architecture. We specialize in digital hardware design for both commercial and aerospace applications

I²C

The I²C-bus is a simple 2-wire serial multi-master bus with collision detection and arbitration. The bus consists of a serial data line (SDA) and a serial clock line (SCL). Aeroflex Gaisler provides both a master core and slave cores.

  • I²C2AHB - I²C to AHB bridge (I²C slave core that provides DMA)
  • I²CMST  - I²C master
  • I²CSLV   - I²C slave core where each transfer is controlled by software