Cobham Gaisler AB provides IP cores and supporting development tools for embedded processors based on the SPARC architecture. We specialize in digital hardware design for both commercial and aerospace applications

Memory controllers

Aeroflex Gaisler provides a wide variety of memory controllers. Some provide a combined interface to several memory types while others only interface a single type. Many of the cores include support for EDAC protection. All controllers use an AHB slave interfaces to the bus and some also include an APB interface for configuration register accesses. Below is an overview of the available controllers. Please see the GRLIB IP cores user's manual for more information about each core.


FTMCTRL - Combined PROM/IO/SRAM/SDRAM Memory controller with EDAC

The FTMCTRL can handle four types of devices: PROM, asynchronous static ram (SRAM), synchronous dynamic ram (SDRAM) and memory mapped I/O devices (I/O). The PROM, SRAM and SDRAM areas can be EDAC-protected using a (39, 7) BCH code. The EDAC provides single error correction and double-error detection for each 32-bit memory word.

The core supports 8-/16- and 32-bit wide PROM,IO and SRAM memories/devices. The SDRAM can either be on the same memory bus as the other memories or on a separate bus. 32-bit wide memories are supported in the former case while the latter supports both 32/64-bits. EDAC for SDRAM is only supported for a 32-bit wide memory bus.

External chip-selects are provided for up to to four PROM banks, one I/O bank, five SRAM banks and two SDRAM banks.

Memory accesses are performed through an AHB slave interface while configuration registers are accessed through an APB interface.

Deliverables

  • VHDL source code
  • Stand-alone testbench
  • User's manual

Area and timing

The FTMCTRL is inherently portable and can be implemented on most FPGA and ASIC technologies. The table below shows the approximate area and frequency on Altera Stratix, Xilinx Virtex2 and ASIC technologies.

(LUTs ) Virtex2 / (ALMs ) Altera

Configuration Stratix Virtex2 ASIC gates
FTMCTRL - - -

The FTMCTRL core can be licensed under a commercial license as part of the GRLIB IP library.


MCTRL - Combined PROM/IO/SRAM/SDRAM Memory controller

The MCTRL supports the same memory types and widths as the FTMCTRL. The differences are that EDAC is not supported and only two PROM chip selects are decoded for the MCTRL.

Deliverables

  • VHDL source code
  • User's manual

Area and timing

The MCTRL is inherently portable and can be implemented on most FPGA and ASIC technologies. The table below shows the approximate area and frequency on Altera Stratix, Xilinx Virtex2, Actel AX/RTAX and ASIC technologies.

(LUTs ) Virtex2 / (ALMs ) Altera/ (Cells) AX/RTAX

Configuration Stratix Virtex2 AX/RTAX ASIC gates
MCTRL without SDRAM support - 350 1000 1500
MCTRL with SDRAM support - 600 1400 2000

The MCTRL core can be licensed under a GPL or commercial license as part of the GRLIB IP library.


FTSRCTRL - PROM/IO/SRAM controller with EDAC

The FTSRCTRL uses a common 32-bit memory bus to interface 32-bit PROM, IO and SRAM devices. 8-bit PROM devices are also supported. It also provides EDAC correcting one and detecting two errors for the PROM and SRAM areas using a (39, 7) BCH code.

One chip select is decoded for the IO-area while SRAM and PROM can have up to 8 chip selects.

Memory accesses are performed through an AHB slave interface while configuration registers are accessed through an APB interface.

Deliverables

  • VHDL source code
  • Stand alone testbench
  • User's manual

Area and timing

The FTSRCTRL is inherently portable and can be implemented on most FPGA and ASIC technologies. The table below shows the approximate area and frequency on Altera Stratix, Xilinx Virtex2, Actel AX/RTAX and ASIC technologies.

(LUTs ) Virtex2 / (ALMs ) Altera/ (Cells) AX/RTAX

Configuration Stratix Virtex2 AX/RTAX ASIC gates
FTSRCTRL - - 700 2500

The FTSRCTRL core can be licensed under a commercial license as part of the GRLIB IP library.


FTSRCTRL8 - 8-bit SRAM/16-bit IO controller with EDAC

The FTSRCTRL8 uses a common 16-bit memory bus to interface 16-bit IO and 8-bit SRAM devices. It also provides EDAC for the SRAM area using a modified (8, 4, 4) Hamming code correcting one and detecting two errors for each 4-bit nibble. This makes the EDAC capable of correcting up to two errors and detecting up to fouor errors per 8-bit data.

One chip select is decoded for the IO-area while SRAM can have up to 8 chip selects.

Memory accesses are performed through an AHB slave interface while configuration registers are accessed through an APB interface.

Deliverables

  • VHDL source code
  • User's manual

Area and timing

The FTSRCTRL8 is inherently portable and can be implemented on most FPGA and ASIC technologies. The table below shows the approximate area and frequency on Altera Stratix, Xilinx Virtex2, Actel AX/RTAX and ASIC technologies.

(LUTs ) Virtex2 / (ALMs ) Altera/ (Cells) AX/RTAX

Configuration Stratix Virtex2 AX/RTAX ASIC gates
FTSRCTRL8 - - 750 -

The FTSRCTRL8 core can be licensed under a commercial license as part of the GRLIB IP library.


SRCTRL - PROM/IO/SRAM controller

The SRCTRL uses a common 32-bit memory bus to interface 32-bit PROM, IO and SRAM devices. 8-bit PROM devices are also supported.

One chip select is decoded for the IO-area, four for SRAM and two for PROM.

Memory accesses are performed through an AHB slave interface while configuration registers are accessed through an APB interface.

Deliverables

  • VHDL source code
  • User's manual

Area and timing

The SRCTRL is inherently portable and can be implemented on most FPGA and ASIC technologies. The table below shows the approximate area and frequency on Altera Stratix, Xilinx Virtex2, Actel AX/RTAX and ASIC technologies.

(LUTs ) Virtex2 / (ALMs ) Altera/ (Cells) AX/RTAX

Configuration Stratix Virtex2 AX/RTAX ASIC gates
SRCTRL - 100 200 500

The SRCTRL core can be licensed under a GPL or commercial license as part of the GRLIB IP library.


FTSDCTRL - 32-/64-bit PC133 SDRAM controller with EDAC

The FTSDCTRL interfaces PC133 SDRAM compatible devices on a 32- or 64-bit wide data bus. It also provides EDAC correcting one and detecting two errors for the PROM and SRAM areas using a (39, 7) BCH code. EDAC is only available for the 32-bit bus configuration.

Chips select decoding is done for two banks.

Both memory and register accesses are performed through an AHB slave interface.

Deliverables

  • VHDL source code
  • User's manual

Area and timing

The FTSDCTRL is inherently portable and can be implemented on most FPGA and ASIC technologies. The table below shows the approximate area and frequency on Altera Stratix, Xilinx Virtex2, Actel AX/RTAX and ASIC technologies.

(LUTs ) Virtex2 / (ALMs ) Altera/ (Cells) AX/RTAX

Configuration Stratix Virtex2 AX/RTAX ASIC gates
FTSDCTRL - - 1000 3500

The FTSDCTRL core can be licensed under a commercial license as part of the GRLIB IP library.


SDCTRL - 32-/64-bit PC133 SDRAM controller

The SDCTRL is identical to the FTSDCTRL except that EDAC is not supported. The SDCTRL also supports mobile SDRAM which the FTSDCTRL does not.

Deliverables

  • VHDL source code
  • User's manual

Area and timing

The SDCTRL is inherently portable and can be implemented on most FPGA and ASIC technologies. The table below shows the approximate area and frequency on Altera Stratix, Xilinx Virtex2, Actel AX/RTAX and ASIC technologies.

(LUTs ) Virtex2 / (ALMs ) Altera/ (Cells) AX/RTAX

Configuration Stratix Virtex2 AX/RTAX ASIC gates
SDCTRL - 300 600 1200

The SDCTRL core can be licensed under a GPL or commercial license as part of the GRLIB IP library.


SSRCTRL - PROM/IO/SSRAM controller

The SSRCTRL uses a common 32-bit memory bus to interface 16-/32-bit PROM, IO and 32-bit Synchronous SRAM devices.

One chip select is decoded for each area,

Memory accesses are performed through an AHB slave interface while configuration registers are accessed through an APB interface.

Deliverables

  • VHDL source code
  • User's manual

Area and timing

The SSRCTRL is inherently portable and can be implemented on most FPGA and ASIC technologies. The table below shows the approximate area and frequency on Altera Stratix, Xilinx Virtex2, Actel AX/RTAX and ASIC technologies.

(LUTs ) Virtex2 / (ALMs ) Altera/ (Cells) AX/RTAX

Configuration Stratix Virtex2 AX/RTAX ASIC gates
SSRCTRL - - - -

The SSRCTRL core can be licensed under a commercial license as part of the GRLIB IP library. Netlists can also be provided under GPL for some technologies.


DDRSPA - 16/32/64-bit DDR266 controller

The DDRSPA can interface two 16,32 or 64-bit wide DDR266 banks. Both memory and configuration register accesses are performed through an AHB slave interface.The core also supports mobile DDR (LPDDR).

Deliverables

  • VHDL source code
  • User's manual

Area and timing

The DDRSPA internally consists of a AHB/DDR controller and a DDR PHY. The controller is inherently portable while the DDR PHY is currently supported on Xilinx Virtex2/Virtex4 and Altera Stratix-II. The table below shows the approximate area and frequency on Altera Stratix, Xilinx Virtex2, Actel AX/RTAX and ASIC technologies.

(LUTs/RAMs ) Virtex2 / (ALMs ) Altera/ (Cells) AX/RTAX

Configuration Stratix Virtex2 AX/RTAX ASIC gates
DDRSPA - 900/2 - -

The DDRSPA core can be licensed under a GPL or commercial license as part of the GRLIB IP library.


DDR2SPA - 16/32/64-bit DDR2 controller

The DDRSPA can interface two 16,32 or 64-bit wide DDR2 banks. Both memory and configuration register accesses are performed through an AHB slave interface.

Deliverables

  • VHDL source code
  • User's manual

Area and timing

The DDR2SPA internally consists of a AHB/DDR2 controller and a DDR PHY. The controller is inherently portable while the DDR2 PHY is currently supported on Xilinx Virtex4/Virtex5 and Altera Stratix-III. The table below shows the approximate area and frequency on Altera Stratix, Xilinx Virtex2, Actel AX/RTAX and ASIC technologies.

(LUTs/RAMs ) Virtex2 / (ALMs ) Altera/ (Cells) AX/RTAX

Configuration Stratix Virtex2 AX/RTAX ASIC gates
DDR2SPA - - - -

The DDR2SPA core can be licensed under a GPL or commercial license as part of the GRLIB IP library.


SPIMCTRL - SPI Memory controller

The core maps a memory device connected via the Serial Peripheral Interface (SPI) into AMBA AHB address space. Reading memory is performed by directly accessing the memory using reads on a AHB slave interface. Other operations, e.g. writes, are performed by sending SPI commands using the core's register interface. The SPIMCTRL supports most SPI Flash devices and also provides limited SPI-mode SD card support.

Deliverables

  • VHDL source code
  • User's manual

Area and timing

The SPIMCTRL is inherently portable and can be implemented on most FPGA and ASIC technologies. The table below shows the approximate area and frequency on Altera Stratix, Xilinx Virtex2, Actel AX/RTAX and ASIC technologies.

(LUTs ) Virtex2 / (ALMs ) Altera/ (Cells) AX/RTAX

Configuration Stratix Virtex2 AX/RTAX ASIC gates
SPIMCTRL 165 300 600 1200

The SPIMCTRL core can be licensed under the GPL or a commercial license as part of the GRLIB IP library.

Reed-Solomon

The Aeroflex Gaisler Reed-Solomon IP cores provide an alternative to traditional Hamming codecs for memory protection - Error Detection And Correction (EDAC) - functionality. The IP cores are specially useful in SDRAM and DDR memory controllers for space applications.

The following Reed-Solomon codecs are available:

  • RS(24, 16, 8, E=1) 16 bit data, 8 check bits, corrects 4-bit error in 1 nibble
  • RS(40, 32, 8, E=1) 32 bit data, 8 check bits, corrects 4-bit error in 1 nibble
  • RS(48, 32, 16, E=1+1) 32 bit data, 16 check bits, corrects 4-bit error in 2 nibbles (when located in separate halves)
  • RS(48, 32, 16, E=2) 32 bit data, 16 check bits, corrects 4-bit error in 2 nibbles