Cobham Gaisler AB provides IP cores and supporting development tools for embedded processors based on the SPARC architecture. We specialize in digital hardware design for both commercial and aerospace applications

GRPCI IP Cores

GRPCI 32-bit master/target PCI interface

The GRPCI IP core provides a 32-bit master/target interface for AMBA AHB-2.0 systems. It includes parameterizable FIFOs for both master and target operation, and can optionally be provided with an independent DMA engine. The GRPCI core is part the GRLIB IP library, and as such provided in full source code under the GNU GPL license. Commercial licensing is also possible, contact This email address is being protected from spambots. You need JavaScript enabled to view it. for more information.

GRPCI features

  • 32-bit PCI interface
  • PCI bus master and target
  • AMBA AHB/APB 2.0 back end interface
  • Configurable FIFOs for both master and target operation
  • Supports incremental bursts and single accesses
  • Bus master capabilities:
    • Memory read, memory write
    • Memory read multiple
    • Memory read line
    • I/O read, I/O write
    • Type 0 and 1 configuration read and write
    • Host bridging
  • Target capabilities:
    • Type 0 configuration space header
    • Configuration read and write
    • Parity generation (PAR)
    • 2 Memory BARs
    • Memory read, memory write
    • Memory read multiple
    • Memory read line
    • Memory write and invalidate
  • Optional DMA engine add on
  • Software support for GRPCI hosts in Linux 2.6, RTEMS and VxWorks

Documentation