Cobham Gaisler AB provides IP cores and supporting development tools for embedded processors based on the SPARC architecture. We specialize in digital hardware design for both commercial and aerospace applications

TSIM2 ERC32/LEON simulator


TSIM is an instruction-level simulator capable of emulating ERC32- and LEON-based computer systems. TSIM provides several unique features:

  • Emulation of ERC32 and LEON2/3/4 processors (in single processor systems)
  • Superior performance: up to 60 MIPS on high-end PC (Intei i7-2600K @3.4GHz)
  • Accelerated processor standby mode, allowing faster-than-realtime simulation speeds
  • Standalone operation, remote connection to GNU debugger (gdb), and library interface
  • 64-bit time for practically unlimited simulation periods
  • Loadable modules to include user-defined I/O devices
  • Instruction trace buffer
  • Stack backtrace with symbolic information
  • Non-intrusive execution time profiling
  • Unlimited number of breakpoints and watchpoints
  • Check-pointing capability to save and restore complete simulator state
  • Code coverage monitoring
  • EDAC operation (ERC32)
  • MMU emulation (LEON3/4)
  • L2 Cache emulation (LEON4)
  • Emulation of GR712RC (one processor emulated), UT699, UT699E, UT700, AT697 and AT7913E (Spw-RTC)

TSIM is available in four configurations: ERC32, LEON2, LEON3 and LEON4 emulation.
Four host platforms are supported: Linux, Linux-x86-64, Solaris and Windows.


TSIM can be run in stand-alone mode, or connected through a network socket to the GNU gdb debugger. In stand-alone mode, a variety of debugging commands are available to allow manipulation of memory contents and registers, breakpoint/watchpoint insertion and performance measurement. Connected to (supported versions of) gdb, TSIM acts as a remote target and supports gdb debug requests. The communication between gdb and TSIM is performed using the gdb extended-remote protocol. Third-party debuggers supporting this protocol can be used.

The screen-shot shows TSIM connected to DDD/gdb (click on image for a larger view).


The simulator time is maintained and incremented according the IU and FPU instruction timing. The parallel execution between the IU and FPU is modelled, as well as stalls due to operand dependencies. Instruction timing has been modelled after the real devices. Integer instructions have a higher accuracy than floating-point instructions due to the somewhat unpredictable operand-dependent timing of the ERC32 and LEON MEIKO FPU. Typical usage patterns have higher accuracy than atypical ones, e.g. having vs. not having caches enabled on LEON systems. The simulator time is maintained using 64-bit values providing virtually unlimited simulation time.

ERC32 emulation

The ERC32 version of TSIM emulates both TSC691/2/3 chip-set and TSC695 from Atmel (was TEMIC). The full behaviour of the devices is accurately emulated, including the memory EDAC functionality. The amount of simulated memory can be configured at run-time. The memory size is limited by the ERC32 architecture: 256KiB - 32MiB RAM, 128KiB - 4MiB ROM. Access to unimplemented MEC registers or non-existing memory will correctly result in a memory exception trap. MEC register parity errors are also emulated when unused register bits are written.

LEON2/3/4 emulation

The functionality of the LEON2, LEON3 or LEON4 VHDL model is emulated, including cache memories, on-chip peripherals and memory controller. The amount of simulated main memory can be configured at run-time. The cache size and organisation can be configured between 1 - 64 KiB/set, 1 - 4 sets, random/LRR/LRU replacement and 8 - 32 bytes/line. The multiplier latency can be programmed for 1 - 35 cycles.

I/O emulation

TSIM has a unique capability to simulate user-defined I/O devices. The user can provide a module emulating an I/O device, which is loaded by TSIM at run-time. The I/O module has access to the simulator event queue, interrupts and other internal data structures, allowing for accurate emulation. Additionally, for LEON2/3/4, there is also an optional AHB I/O module interface, that replaces the internally simulated AHB bus,  making adding or replacing peripheral devices connected to the on-chip AHB bus possible. Both types of I/O modules are typically written in C, and can use any features of the host operating system. This provides high simulation performance and capability to communicate with any other framework (e.g. such as EUROSIM or SIMSAT). A report describing the emulation of an ERC32-specific ASIC can be found here.

Device emulation

To simplify emulation of existing LEON2/3 devices, TSIM includes modules (in the matching LEON-version of TSIM) to functionally emulate the I/O cores in the following devices:

  • AT697:       InSilicon PCI interface (master/target)
  • GR712:       SpaceWire, Ethernet, CAN, GPIO, AHBRAM, SPI, GRTIMER, 6xUART
  • UT699/E:    SpaceWire, PCI, Ethernet, CAN, GPIO
  • UT700:       SpaceWire, PCI, Ethernet, CAN, GPIO, SPI
  • AT7913E:   SpaceWire, CAN, FIFO, on-chip RAM, ADC/DAC, GPIO (only available as a separate product)

TSIM as Library

TSIM can also be provided as a static library (DLL for Windows), which can be linked into a larger user applications. The library supports all TSIM commands and operations and additionally provides access to  some CPU model internals. The loadable I/O module interface is provided in the same manner when using TSIM as a library  as when running TSIM standalone.


The TSIM profiling function calculates the amount of (target processor) execution time spent in each function of the emulated application. This is done in a non-intrusive manner and without instrumenting the code. The profiling data is printed as a sorted list of execution time per sub-program:

function samples ratio(%)

start 36144 100.00
_start 36144 100.00
main 36134 99.97
Proc_1 10476 28.98
Func_2 9885 27.34
strcmp 8161 22.57
Proc_8 2641 7.30
.div 2097 5.80
Proc_6 1412 3.90
Proc_3 1321 3.65
Proc_2 1187 3.28
.umul 1092 3.02
Func_1 777 2.14

Code coverage monitoring

The TSIM code coverage support will monitor all internally emulated processor memory (PROM, SRAM and SDRAM). The coverege support does not cover memory implemented in I/O modules or AHB modules. When coverage is enabled, TSIM registers whether a memory location has been read, written or executed. The coverage information can be displayed on the TSIM console or dumped to a file for batch post processing. When coverage is enabled, the simulation performance is decreased compared running TSIM with coverage disabled.

tsim> cov en
coverage enabled:
0x00000000 - 0x00200000 : rom
0x02000000 - 0x02400000 : ram
tsim> go
resuming at 0x02000000
Perm Towers Queens Intmm Mm Puzzle Quick Bubble Tree FFT
100 133 83 267 150 633 83 167 550 267
Nonfloating point composite is 315
Floating point composite is 478
Program exited normally.
tsim> cov pr Fft
02003840 : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
020038c0 : 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
02003940 : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1
020039c0 : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
02003a40 : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


TSIM is highly optimised for speed and provides simulation performance of more than 1 MIPS / 100 MHz (host cpu frequency). On a high-end PC running Linux, real-time operation of a 25 MHz, 0-ws ERC32 system can readily be achieved. TSIM can also accelerate simulation time when the emulated application is in idle mode. The more time the CPU is spent in idle mode, the more real time simulation speedup. A collection of performance statistics are automatically calculated and can be displayed with the 'perf' command:

Cycles : 101917302
Instructions : 64311375
Overall CPI : 1.58
CPU performance (20.0 MHz) : 12.62 MOPS (12.62 MIPS, 0.00 MFLOPS)
Simulated time : 5.10 s
Processor utilisation : 100.00 %
Real-time performance : 167.90 %
Simulator performance : 21189.60 KIPS
Used time (sys + user) : 3.04 s

The following table shows the performance of TSIM-ERC32 on certain platforms in terms of raw MIPS and in relation to real ERC32 hardware running at 14 MHz (100% cpu load).

TSIM ERC32 Professional Dhrystone CPI 1.5 GTB CPI 2.6, 15% float
Platform Raw MIPS Rel. perf. Raw MOPS Rel. perf.
Real ERC32 hardware, 14 MHz
9.3 MIPS 100% 6.8 MOPS 100%
3.0 GHz Intel Core2 (E8400), 6 MiB cache 42 MIPS  450%  40 MOPS  580%
2.2 GHz AMD64 (3400+), 1 MiB cache 25 MIPS 260% 20 MOPS 300%
3.0 GHz Xeon, 0.5 MiB cache
22 MIPS 230% 10 MOPS 190%
2.8 GHz P4, 0.5 MiB cache 20 MIPS 200% 9.5 MOPS 175%
1.6 GHz Centrino, 1 MiB cache 17 MIPS 175% 12 MOPS 225%

 Host support

TSIM is available for Sun Solaris (SPARC), Linux (32-bit), Linux-x64 (64-bit) and Windows XP/7.

Users and projects

More than 400 commercial TSIM licenses have been sold and are being used in various LEON and ERC32 projects. Many more copies of the evaluation version of TSIM are used by individuals and universities. TSIM is the market leader for ERC32 and LEON simulation, and used in major space projects such as Cryosat, ATV, Beagle-2, Ariane-5, GOCE, Herschel/Planck, PROBA-2 and many others.

Evaluation version

An evaluation version of TSIM/LEON3 is available from the download page. It is limited to 32-bit time and and does not support check-pointing, loadable modules, library interface, code coverage, configuration of caches or configuration of memory.


To download TSIM or the user's manual, please proceed to the download page.