Cobham Gaisler AB provides IP cores and supporting development tools for embedded processors based on the SPARC architecture. We specialize in digital hardware design for both commercial and aerospace applications

Gaisler Research will attended DASIA 2008. Exhibiting and presenting at Hotel Melià Palas Atenea, Palma de Majorca, Spain on the 27-30th of May.

LEON processor in focus at DASIA 2008 conference in Palma, Spain

The international space system engineering conference DASIA 2008 (DAta Systems In Aerospace) was held this year in May in Palma, Spain. The LEON processor and related tools were discussed in about twenty oral presentations during the conference.

A full session was dedicated to LEON based processors, during which Gaisler Research presented a wide range of applications in which the LEON processor is being used, covering amongst others the fault-tolerant LEON3-FT processor being implemented in 180 nm technology and a brand new hardware accelerated instruction simulator for the LEON2-FT processor.
 

 - "This conference corroborates Gaisler Research's position as the leading supplier of high performance processor IP solutions and simulation tools to the space industry", says Sandi Habinc, Vice President at Gaisler Research AB.

 

Special LEON session

Gaisler Research presented the development of a fault-tolerant design featuring their high performance LEON3-FT based processor with high-performance fully pipelined floating-point-unit and SPARC reference memory management unit, together with high-speed SpaceWire links and CAN interface. The processor will be manufactured on the UMC process using the DARE library developed by IMEC, Belgium. The Design Against Radiation Effects (DARE) library uses the standard 180 nm UMC ASIC flow and provides protection of logic and registers.

Gaisler Research presented their hardware accelerated instruction simulator for the AT697F device from Atmel, France. The AT697F device has been designed using the fault-tolerant LEON2-FT VHDL model that has been developed in co-operation between the European Space Agency (ESA) and Gaisler Research. The TSIM-HW simulator can simulate AT697F based system at better than real-time performance, which has previously not been possible with software-only based simulators.

ASTRIUM Satellites, France, presented their LEON2 Software Validation Facility, which is based on a hardware accelerated instruction simulator for LEON2-FT.

ASTRIUM ST, Germany, presented their ERNObox that is based on the LEON2-FT AT697F device. The ERNObox is currently in orbit, flying on the European Columbus space laboratory that is part of the International Space Station (ISS)

Thales Alenia Space, Italy, presented their development of a real-time AOCS application based on the LEON3 processor. The design is based on the GRLIB IP core library from Gaisler Research and encompasses the LEON3 processor and floating-point unit, multiple SpaceWire interfaces and a 10/100 Ethernet MAC. The processor communicates with a startracker head via the SpaceWire interface.


Other Gaisler Research presentations

The European Space Agency (ESA), Gaisler Research and Saab Space presented the development of the SpaceWire-RTC ASIC. The SpaceWire-RTC is considered as a key ASSP in future ESA satellite developments. The ASIC is based on the LEON2-FT processor, with several IP cores from Gaisler Research. Gaisler Research has performed the overall logical design of the ASIC and has been in charge for the subsequent FPGA and ASIC validation

Gaisler Research presented their development suite for the above SpaceWire-RTC ASIC. The suite comprises a hardware board (with or without housing) featuring the ASIC together with memory and interface drivers. The suite also comprises support for the SpaceWire-RTC in the RTEMS and VxWorks operating systems, as well as a loadable module for the TSIM instruction simulator.

Gaisler Research presented the RASTA (Reference Avionics System Test-bench Activity) initiative that has been started by ESA, with the aim to simplify integration of avionics and payload equipment. Gaisler Research has developed the hardware elements for RASTA, based on the GRLIB IP core library from Gaisler Research. The latest contribution was the UT699RH LEON3-FT development board.

 

Other presentations

The European Space Agency (ESA) started off the conference by presenting its long-term strategy for the use of the SpaceWire link interface standard. Both LEON2-FT and LEON3-FT from Gaisler Research were identified as key elements in this strategy.

Kayser-Threde, Germany, presented their new payload handling system for the German TET satellite. The equipment is based on the LEON3-FT processor from Gaisler Research, implemented in an FPGA.

IDA TU Braunschweig, Germany, presented their new architecture for advanced system-on-chip design with in-flight reconfigurable processing cores. The design includes the LEON3 processor from Gaisler Research, implemented in a reconfigurable FPGA.

SciSys, UK, presented their CCSDS SOIS implementation, which is based on the RASTA hardware equipment from Gaisler Research. The specific RASTA equipment is built on a miniature CompactPCI crate with FPGA development boards implementing the LEON2 processor and crucial interfaces.

European Space Agency (ESA), Netherlands, presented their efforts in the implementation of the CCSDS file delivery protocol, which has been done using the LEON2 based RASTA equipment from Gaisler Research.

Astrium, Germany, presented their ASIC building blocks for space applications. One of their ASICs is based on the LEON2-FT processor using the GRPFU high-performance fully pipelined floating-point-unit from Gaisler Research.

Saab Space, Sweden, presented their COLE system-on-chip ASIC, which is based on the LEON2-FT processor using the SPARC reference memory management unit from Gaisler Research.

Ramon-Chip, Israel, presented their RadSafe library, which provides rad-hard capability using commercial 180 nm CMOS technology. One of the test devices is based on the LEON3 processor from Gaisler Research.

IHP, Germany, presented their library, which provides rad-hard capability using commercial 250 nm CMOS technology. One of the test devices is based on the LEON3 processor from Gaisler Research.

Critical Software, Portugal, presented the xLuna demonstrator for the ESA Mars rover, based on the LEON2 processor with the SPARC reference memory management unit from Gaisler Research.

Edisoft, Portugal, presented their work in supporting RTEMS for the LEON2 processor.

European Space Agency (ESA), Netherlands, presented their advanced mass memory concept development, which uses the LEON2-FT core processor as the controller.

 

References

The conference is organised by EUROSPACE, an association of the European space industry, in co-operation with the European Space Agency (ESA), among others.

DASIA 2008 (DAta Systems In Aerospace) - Programme, SP-655 Abstracts