TSIM3 GR716 simulates the GR716A LEON3FT and GR716B LEON3FT microcontrollers that has been developed by us. GR716A and GR716B simulation is possible using a TSIM3-LEON3 license or a dedicated TSIM3-GR716 license at a reduced price.

TSIM GR716 includes functionality such as:

• Emulation of the LEON3 in the GR716A and GR716B microcontrollers
• FPU emulation
• Standalone Tcl frontend for both automation and interactive use, with tab completion
• Provided as a library to be included in larger simulator frameworks (TLIB)
• Source level debugging via remote connection from GNU Debugger (GDB) with GDB 8.2 support
• 64-bit time for practically unlimited simulation periods
• Detailed device register information down to individual register fields
• Detailed instruction tracing with instruction results and symbolic information
• Detailed AMBA bus tracing that can be presented combined with instruction tracing
• Memory emulation, including SRAM, PROM, SPI memories, local data RAM, and local instruction RAM.
• Loadable modules to include user-defined device models
• Non-intrusive execution time profiling
• Non-intrusive code coverage monitoring
• Stack backtrace with symbolic information
• Unlimited number of breakpoints and watchpoints
• Checkpointing capability, to save and restore complete simulator state
• Detailed built-in help for both commands and start options

Two host platforms are supported: Linux and Windows 10.

• TSIM User's Manual

Usage

TSIM can be run in stand-alone mode, or connected through a network socket to the GNU Debugger (GDB). In stand-alone mode, a variety of debugging commands are available to allow manipulation of memory contents and registers, breakpoint/watchpoint insertion, performance measurements, instruction traces and bus traces. Connected to (supported versions of) GDB, TSIM acts as a remote target and supports GDB debug requests. The communication between GDB and TSIM is performed using the GDB extended-remote protocol. Third-party debuggers supporting this protocol can be used.

The screenshot shows Eclipse connected to TSIM via GDB (click on image for a larger view).

Timing

The simulator time is maintained and incremented according the IU and FPU instruction timing. The parallel execution between the IU and FPU is modelled, as well as stalls due to operand dependencies. Instruction timing has been modelled after the real devices. Integer instructions have a higher accuracy than floating-point instructions due to the somewhat unpredictable operand-dependent timing of the FPU. Typical usage patterns have higher accuracy than atypical ones. The simulator time is maintained using 64-bit values providing virtually unlimited simulation time.

GR716A emulation

The functionality of the GR716A LEON3 VHDL model is emulated, including on-chip peripherals and I/O cores such as:

• SpaceWire, CAN, GPIO, FTMCTRL, Boot ROM, SPI, SPIM, GPTIMER, UART, DAC etc.

Additional GR716A features include:

• Ability to boot from SPIM, SRAM and PROM
• Atomic access support for all APB registers and local data RAM (AND, OR, XOR, Set&Clear).

GR716B emulation

The functionality of the GR716B LEON3 VHDL model is emulated, including on-chip peripherals and I/O cores such as:

• SpaceWire Router, CANFD, GPIO, FTMCTRL, Boot ROM, SPI, SPIM, GPTIMER, UART, DAC, etc.

Additional GR716B features include:

• Ability to boot from SPIM, SRAM and PROM and use WMEM sections
• Real-Time Accelerators (RTA) supported through user modules, example included.

AHB and I/O emulation

TSIM has the capability to be extended with user-defined modules. This can be used to add simulation models of AHB and I/O devices as well as models connected to interfaces simulated by TSIM, such as GPIO, SPI and CAN. Such modules are loaded by TSIM at run-time. The modules has access to the simulator event queue, interrupts and other internal data structures, allowing for accurate emulation.  Modules are typically written in C, and can use any features of the host operating system. This provides high simulation performance and capability to communicate with any other framework (e.g. such as EUROSIM or SIMSAT).

Profiling

The TSIM profiling function calculates the amount of execution time spent in and under each subroutine of the simulated program. The profiling is non-intrusive. The Profiling does not have any affect on the execution in terms of simulated time and no changes needs to be done to the instrumented code. The profiling information is printed as a list sorted on highest execution time ratio:

tsim> load dhrystone.elf

...
tsim> profile 1
  profiling enabled, sample period 1000
tsim> run
...
tsim> profile
  function      ratio(%)
  __bcc_crt0      100.00
  main             99.35
  Func_2           31.04
  strcmp           26.97
  memcpy           17.34
  Proc_8            7.70
  Func_1            5.13
  Proc_7            4.49
  Proc_6            1.92
tsim>

Code coverage monitoring

The TSIM code coverage support will monitor all internally emulated processor memory. The coverage support also monitors the  AHBROM and SPIM cores. When coverage is enabled, TSIM registers whether a memory location has been read, written or executed. The coverage information can be displayed on the TSIM console or dumped to a file for batch post processing. When coverage is enabled, the simulation performance is decreased compared running TSIM with coverage disabled.

tsim> cov en
  coverage enabled:
  0x01000000 - 0x01200000  : ROM
  0x40000000 - 0x40400000  : SRAM
  0x00000000 - 0x00100000  : AHBROM
  0x30000000 - 0x30010000  : DLRAM
  0x31000000 - 0x31020000  : ILRAM
  0x02000000 - 0x04000000  : SPIM0
  0x04000000 - 0x06000000  : SPIM1
tsim> cov print strcmp
  31004198 : 1  1 11  0  1  1  1 11  0  1  1  1  1  1  1  1
  310041d8 : 9  1  0  0  1  1  1 11  0  1  1  1  1 19  1  1
  31004218 : 1 11  1  1  1  9  1  0  0  1  1 19  1  1  1  1
  31004258 : 1  9  1  0  0  0  0  1  1  1  0  0  1  9  1  0
  31004298 : 0  0  0  0  0  0  0  0  0  0  0  0  1  1  1  1
  310042d8 : 1  1  1  1  9  1  0  0  0  0  0  0  0  0  0  0
  31004318 : 0  0  0  0  1  1 19  1  1  1  0  0  0  0  0  0
  31004358 : 0  0  0  0  0  0  0  0  0  0  4  0  0  0  0  0
  31004398 : 0  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
  310043d8 : 0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
  31004418 : 0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
  31004458 : 4  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
  31004498 : 0  0  0  0  0  0  0  1  1  1  1  1  1  1  1  1
  310044d8 : 1 11  1  1  1 11  1  1  1  1 11  0  1  1  1 11
  31004518 : 1  1  1 11  0  1  1  1 19  1  1  1  1  1  1  1
  31004558 : 11  1  1  1 19  1  1 11 0  1  1  1  1  1  1  1