AES 128

The input and output for the AES algorithm each consist of sequences of 128 bits (digits with values of 0 or 1). These sequences will sometimes be referred to as blocks and the number of bits they contain will be referred to as their length. The cipher key for the AES-128 algorithm is a sequence of 128 bits (can also be 192 or 256 bits for other algorithms).

To transfer a 128 bit key or data block four write operations are necessary since the bus interface is 32 bit wide. After supplying a “key will be input” command to the control register, the key is input via four registers. After supplying a “data will be input” command to the control register, the input data is written via four registers. After the last input data register is written, the encryption or decryption is started. The progress can be observed via the debug register. When the operation is completed, an interrupt is generated. The output data is then read out via four registers. Note that the above sequence must be respected. It is not required to write a new key between each data input. There is no command needed for reading out the result.

The implementation requires around 89 clock cycles for a 128 bit data block in encryption direction and around 90 clock cycles for decryption direction. For decryption an initial key calculation is required. This takes around 10 additional clock cycles per every new key. Typically large amounts of data are decrypted (and also encrypted) with the same key. The key initialization for the decryption round does not influence the throughput.

The IP can be implemented in any ASIC or FPGA technology. For specific information related to Xilinx, Microchip, and Lattice FPGAs, please refer to our dedicated web pages:

• Specific support for Lattice FPGAs
• Specific support for Microchip FPGAs
• Specific support for Xilinx FPGAs

Estimation of the resource utilization can be found here: Excel sheet for SoC area estimation

‍

‍

The IP core is available as a separate package or as an addition to commercial versions of the GRLIB VHDL library.

Contact sales@gaisler.com for licensing information.

The core is available in two configurations:

GRAES_DMA: A DMA based on an AMBA AHB master interface automatically fetches from memory the encryption key, initialization vector and plaintext

GRAES: Encryption key, initialization vector and plaintex are provided to the IP core trough an AMBA AHB slave interface