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NAND Flash
Status:
Available
NANDFCTRL2 is a VHDL IP core implementing a NAND flash memory controller designed to operate with ONFI 4.0 devices and providing DMA transfers to and from the NAND flash memory.
Overview
The memory controller is designed to operate with ONFI 4.0 flash memory devices and provides DMA transfers to and from the memory.
The core is suitable for users who want to include NANDFCTRL2 in products and is suitable for both ASIC and FPGA implementations.
The IP is suitable for SLC-based flight-grade Raw NAND Flash interfaces, with the exception for the flight assurance related to the FPGA PHY implementation.
Future implementations are pending customer demands and include hardware LDPC ECC for supporting MLC and TLC modes.
Architecture
Key Tech Spec
Target technology support
Evaluation boards
Ordering information
Development Kit
Licensing
Software
Tools
Block diagram
Supported Hardware
Configuration
Reference Design
Other resources
Detailed features
ONFI 4.0 support
- All mandatory ONFI 4.0 commands + optional and vendor-specific commands
- Asynchronous / SDR data interface (all timing modes including EDO)
- Synchronous interfaces: NV-DDR2 and NV-DDR3 (timing modes 0-10)
- Preliminary technology-independent PHY
- The attainable timing mode depends on the target technology
Other features
- BCH EDAC with up to 60 bits correction capacity per 1024 bytes chunks of data
- Randomization of memory data
- Support to read flash memory soft bits to enable a software LDPC implementation
- Fault tolerance features
- Basic timeout-based SEFI detection and reporting
- 8-bit data interface with support for up to 64 targets and 16 channels (16x 8 bits data channels)
Downloads
File
Category
Revision
Date
Access
Data sheet and user's manual
2024.2
2024-07-15
Free download
Password/
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Data sheet and user's manual
1.0
2023-09-01
Free download
Password/
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Data sheet and user's manual
1.0
2023-09-01
Free download
Password/
Contact us
Frequently asked questions
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