CAN FD

The codec is compliant with the ISO standard for CAN-FD: 11898-1:2015 (2nd edition). It implements the functionality related to the PL and MAC sub-layers of the protocol: transmission, reception and acknowledgment of frames, bit synchronization, CRC calculation, error detection and signaling, arbitration control, frame encoding, etc. It supports both classical CAN and CAN-FD frames, including all the types (Data, Remote, Error and Overload Frames) and formats (CBFF, CEFF, FBFF and FEFF) specified in the standard.

The Transmit and Receive Channels operate separately. GRCANFD includes a FIFO for each channel in order to temporarily buffer frames; the size of these FIFOs can be individually configured via VHDL generics. For the Transmit Channel, GRCANFD fetches frames from the external memory and stores them internally into the TX FIFO; frames are then transmitted by the codec according to the CAN-FD standard. For the Receive Channel, the codec verifies and acknowledges the frames, and GRCANFD filters and stores them into the RX FIFO; once a full frame is available, GRCANFD writes it to the external memory. The communication with the external memory is handled by an autonomous DMA engine transferring frames over the generic bus master interface.

The IP can be implemented in any ASIC or FPGA technology. For specific information related to Xilinx, Microchip, and Lattice FPGAs, please refer to our dedicated web pages:

• Specific support for Lattice FPGAs
• Specific support for Microchip FPGAs
• Specific support for Xilinx FPGAs

Estimation of the resource utilization can be found here: Excel sheet for SoC area estimation

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The IP core is available as a separate package or as an addition to commercial versions of the GRLIB VHDL library.

Contact sales@gaisler.com for licensing information

Device drivers for RTEMS and VxWorks are available for all CAN cores.