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SpaceFibre and WizardLink Interface
Status:
Available
The GRHSSL IP Core is a versatile and highly configurable high-speed serial link controller written in VHDL, capable of implementing a SpaceFibre IP Core (GRSPFI), a WizardLink IP Core (GRWIZL), or both within a single solution.
Overview
GRHSSL is a highly configurable IP that can instantiate a SpaceFibre controller, a WizardLink controller or both. Both controllers share a DMA engine that handles the communication between the IP and external memory via hardware descriptors. GRHSSL shall be connected to a SerDes macro, that can be located either on-chip or externally. Adapters for AMBA AHB 2.0 and AXI 4 are available.
Additionally, the SpaceWire router can be integrated with the SpaceFibre controller. SpaceFibre ports can be connected to the internal FIFO ports of the SpaceWire router to bridge between SpaceWire and SpaceFibre traffic. SpaceWire data from/to multiple payloads can be aggregated in a single SpaceFibre High Speed Serial Link, all without software intervention.
Architecture
Key Tech Spec
Target technology support
Evaluation boards
Ordering information
Development Kit
Licensing
Software
Tools
Block diagram
Supported Hardware
Configuration
Reference Design
Other resources
Detailed features
- SpaceFibre codec designed according to the SpaceFibre specification ECSS-E-ST-50-11C, single-lane implementation
- WizardLink codec designed to interface with Texas Instrument TLK2711 transceiver
- The IP can inter-operate with off-chip SerDes devices or with FPGA/ASIC hard macros
- Optional 8b10b encoding
- Support for wide (36/40) or narrow (16/20) SerDes interfaces
- Configurable number of DMA channels
- Optional SpaceFibre RMAP support
- Optional fault tolerant features
- Support for both big-endian and little-endian systems
Downloads
File
Category
Revision
Date
Access
Data sheet and user's manual
2024.2
2024-07-15
Free download
Password/
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Frequently asked questions
What is WizardLink?
Whats is SpaceFibre?
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