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NOEL-V
Status:
Available
The NOEL-V is a synthesizable VHDL model of a processor that implements the RISC-V architecture. The NOEL-V can be implemented as a dual-issue processor, allowing up to two instructions per cycle to be executed in parallel.
Overview
The NOEL-V is designed for space applications, with a high-performance and fault-tolerant design. Built on the RISC-V architecture, NOEL-V offers flexibility and customization options, allowing SoC designers to create solutions tailored to their specific needs. Software developers have access to a vast library of existing software and tools to help them create the perfect solution.
Architecture
Key Tech Spec
Target technology support
Evaluation boards
Ordering information
Development Kit
Licensing
Software
Tools
Block diagram
Supported Hardware
Configuration
Reference Design
Other resources
Detailed features
The NOEL-V processor can implement the following features:
- RISC-V 32-bit and 64-bit architecture
- Hardware multiply and divide units
- Compressed (16 bit) instruction support
- Atomic instruction extension
- 32/64 bit floating point extensions using non-pipelined area efficient FPU or high-performance fully pipelined IEEE-754 FPU
- Machine, supervisor and user mode.
- RISC-V standard MMU with configurable TLB
- RISC-V Hypervisor (H) extension (adding virtual supervisor mode and virtual user mode)
- Fault Tolerance
- Robust and fully synchronous single-edge clock design
- Large range of software tools: compilers, kernels and debug monitors
- High Performance*: CoreMark: 4.03** / 4.69*** CoreMark/MHz
- *For HPP64 configuration. CoreMark score varies with processor configuration, microarchitectural changes, and toolchains.
- **-march=rv64im-mabi=lp64 -O2 -funroll-all-loops -funswitch-loops -fgcse-after-reload-fpredictive-commoning -mtune=sifive-7-series-finline-functionsfipa-cp-clone -falign-functions=8 -falign-loops=8 -falign-jumps=8 --param max-inline-insns-auto=20 using GCC 9.2.0 under RTEMS 5
- *** Using "#define ee_u32 int32_t" in core_portme.h, as is common for 64 bit RISC-V.
- RISC-V standard APLIC
- RISC-V standard PMP (physical memory protection)
- RISC-V standard external debug support
- RISC-V watchdog
- RISC-V IOMMU
- Support for RISC-V bit manipulation extensions: Zba/b/c/s, Zbkb/c/x
- Support for counter interrupt RISC-V extensions: Sscofpmf
- Support for cache management operations RISC-V extension: Zicbom
- Support for Sstc RISC-V extension
- Advanced dual-issue in-order pipeline
- Dynamic branch prediction, branch target buffer and return address stack
- Four full ALUs, two of them late in the pipeline to reduce stalls
- Separate instruction and data L1 cache (Harvard architecture) with snooping
- Optional L2 cache: 256-bit internal, 1-4 ways, 16 KiB - 8 MiB
- Native AMBA 2.0 AHB bus interface, 32-, 64- or 128-bit wide
- Subsystem including processor and Level-2 cache with AXI4 backend also available.
Downloads
File
Category
Revision
Date
Access
Data sheet and user's manual
2024.2
2024-07-15
Free download
Password/
Contact us
Data sheet and user's manual
2024.2
2024-07-15
Free download
Password/
Contact us
Frequently asked questions
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