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GR712RC
Status:
TRL 9
The GR712RC is a radiation hardened dual-core fault-tolerant LEON3FT SPARC V8 microprocessor, offering high reliability, low power consumption, and many communication interfaces. The GR712RC is included in the European Preferred Parts List (EPPL).
Overview
The GR712RC is a dual-core LEON3FT SPARC V8 processor, with advanced interface protocols, designed for high-reliability aerospace applications. The GR712RC is fabricated at Tower Semiconductors Ltd., using standard 180 nm CMOS technology. It employs our radiation-hard-by-design methods and the RadSafeTM technology from Ramon Space, enabling superior radiation hardness and excellent low-power performance.
The GR712RC provides a rich variation of communications interfaces to allow different systems to be implemented using the same device type, thereby simplifying parts procurement. It also brings cost reductions to software development since the core functionality can be reused from application to application, only changing the drivers for the interfaces.
Architecture
Key Tech Spec
Target technology support
Evaluation boards
Ordering information
Development Kit
Licensing
Software
Tools
Block diagram
Supported Hardware
Configuration
Reference Design
Other resources
Detailed features
- Two LEON3FT SPARC V8 compliant 32-bit processors, each with:
- SPARC reference memory management unit (SRMMU) with 32 TLB entries
- High-performance double-precision IEEE-754 floating point co-processor (GRFPU)
- 16 KiB multi-way instruction cache and 16 KiB multi-way data cache
- caches have EDAC (detection by parity, correction by refetch)
- Internal on-chip high speed AMBA (AHB) bus
- Instruction trace and AMBA (AHB) trace buffers for debugging
- Timer unit with four 32-bit timers including watchdog
- Secondary timer unit with two 32-bit timers
- Primary and secondary interrupt controller for 31 interrupts
- On-chip 192 kByte memory block with EDAC
- External memory support:
- Data bus widths:
- 8 bits data + 7 bits for EDAC checkbits
- 16 bits data
- 32 bit data + 16 bits for EDAC checkbits
- 8 bit BCH EDAC for SRAM and PROM, 16 bit Reed-Solomon EDAC for SDRAM
- Memory types: SRAM, SDRAM, FLASH PROM / EEPROM and parallel I/O
- Programmable wait-states: SRAM read/write cycle 2 - 5 clock cycles
- PROM / EEPROM / NOR-FLASH read cycle 2 - 32 clock periods
- Data bus widths:
- Debug Support Unit (DSU) accessed via JTAG and SpaceWire RMAP targets
- Six SpaceWire ports, maximum 200 Mbps full-duplex data rate
- Of which 2 implement RMAP targets
- Configurable I/O selection matrix, connecting a subset of available I/O units to 67 shared pins:
- Four SpaceWire ports, maximum 200 Mbps full-duplex data rate
- Redundant MIL-STD-1553B BRM (BC/RT/BM) interface
- Two CAN 2.0B bus controllers
- Six UART ports, with 8-byte FIFO
- Ethernet MAC with RMII 10/100 Mbps port
- SPI master serial port
- I2C master serial port
- ASCS16 (STR) serial port
- SLINK 6 MHz serial port
- CCSDS/ECSS 5-channel Telecommand decoder, 10 Mbps input rate
- CCSDS/ECSS Telemetry encoder, 50 Mbps output rate
- 26 input and 38 input/output general purpose ports
Downloads
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Revision
Date
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Technical specification
latest
2023-08-07
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Application note
2.1
2017-05-23
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1.0
2017-04-21
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1.1
2017-08-17
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1.0
2017-10-28
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1.0
2015-11-26
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1.0
2015-11-30
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1.0
2018-04-17
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1.0
2018-04-17
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Technical note
1
2017-01-11
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1
2017-01-11
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1
2015-10-27
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Technical note
1.1
2022-10-01
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1.0
2017-10-15
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1.0
2015-10-29
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1.1
2017-06-15
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1.5
2018-04-12
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1.3
2017-12-21
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1.3
2017-12-21
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1.0
2019-02-28
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1.1
2020-09-22
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1.1
2022-10-12
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Frequently asked questions
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