SpaceWire node

The complete documentation is found in the GRSPW2_PHY section of GRLIB IP Core User’s Manual.

The main sub-blocks of the core are the link interface, the RMAP target and the AMBA interface. The link interface consists of the receiver, transmitter, and the link interface FSM. They handle comunication on the SpaceWire network. The PHY block provides a common interface for the receiver to the four different data recovery schemes and is external to this core. The AMBA interface consists of the DMA engines, the AHB master interface and the APB interface. The link interface provides FIFO interfaces to the DMA engines. These FIFOs are used to transfer N-Chars between the AMBA and SpaceWire domains during reception and transmission.

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The RMAP target is an optional part of the core which can be enabled with a VHDL generic. The RMAP target handles incoming packets which are determined to be RMAP commands instead of the receiver DMA engine. The RMAP command is decoded and if it is valid, the operation is performed on the AHB bus. If a reply was requested it is automatically transmitted back to the source by the RMAP transmitter.

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The IP can be implemented in any ASIC or FPGA technology. For specific information related to Xilinx, Microchip, and Lattice FPGAs, please refer to our dedicated web pages:

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- Specific support for Lattice FPGAs
- Specific support for Microchip FPGAs
- Specific support for Xilinx FPGAs

Estimation of the resource utilization can be found in the download files below (Excel sheet for SoC area estimation).

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The IP core is available as a separate package or as an addition to commercial versions of the GRLIB VHDL library. Contact sales@gaisler.com for licensing information

Software drivers supporting the IP are available for bare-metal, RTEMS, VxWorks and Linux.

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GRSPW2 is the successor to the GRSPW. It is based on the old core and contains all of its functionality and features while also adding new ones. The major differences are shown in the table below.
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Feature                   GRSPW                   GRSPW2
RMAP                   Draft C                 Draft F
Clock factor         4                          8
DMA channels     1                           4
Timers                 System clock       SpaceWire clock
Addressing         Single address     Multiple addresses and ranges

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• GRPSW2 implements RMAP error code 12 (Invalid destination logical address) which is the only part missing in GRSPW (not making it draft F compliant).
• The clock factor is the largest difference in clock frequency between the AHB clock and the SpaceWire clock. GRSPW2 has doubled this factor.
• Up to four DMA channels can be implemented in GRSPW2 while the old core only supports one.
• The GRSPW required configuration of the disconnect and 6.4 us timers since they used the system clock. The new core uses the SpaceWire transmit clock which makes that extra configuration step unnecessary.
• GRSPW2 supports separate logical addresses for each DMA channel with a corresponding mask that can be used to disable individual bits during address comparison effectively creating address ranges.

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