TSIM3

TSIM can operate in three modes: standalone, used as a library and attached to GDB. In standalone mode, LEON applications can be loaded and simulated using a scriptable Tcl based command line interface. A number of commands are available to drive, investigate and interact with the simulation. When TSIM is used is a library. TSIM can be driven via a C API. This API makes standalone commands available as well as additional functionality. When attached to GDB, TSIM acts as a remote GDB target. Applications are loaded and debugged through GDB (or a GDB front-end such as Eclipse or Visual Code). It this mode it is also possible to use the standalone commands.

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Usage

TSIM can be run in stand-alone mode, or connected through a network socket to the GNU Debugger (GDB). In stand-alone mode, a variety of debugging commands are available to allow manipulation of memory contents and registers, breakpoint/watchpoint insertion, performance measurements, instruction traces and bus traces. Connected to (supported versions of) GDB, TSIM acts as a remote target and supports GDB debug requests. The communication between GDB and TSIM is performed using the GDB extended-remote protocol. Third-party debuggers supporting this protocol can be used. The screenshot shows Eclipse connected to TSIM via GDB.

Timing

The simulator time is maintained and incremented according the IU and FPU instruction timing. The parallel execution between the IU and FPU is modelled, as well as stalls due to operand dependencies. Instruction timing has been modelled after the real devices. Integer instructions have a higher accuracy than floating-point instructions due to the somewhat unpredictable operand-dependent timing of the FPU. Typical usage patterns have higher accuracy than atypical ones. The simulator time is maintained using 64-bit values providing virtually unlimited simulation time.

AHB and I/O emulation

TSIM has the capability to be extended with user-defined modules. This can be used to add simulation models of AHB and I/O devices as well as models connected to interfaces simulated by TSIM, such as GPIO and SPI. Such modules are loaded by TSIM at run-time. The modules has access to the simulator event queue, interrupts and other internal data structures, allowing for accurate emulation.  Modules are typically written in C, and can use any features of the host operating system. This provides high simulation performance and capability to communicate with any other framework (e.g. such as EUROSIM or SIMSAT).

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• TSIM3 is licensed per processor architecture (LEONx)
  • The license includes all the I/O models available for the supported SoCs. See documentation for details.
• There is also a license limited to the GR716 at a reduced price
• An evaluation license is available for non-commercial usage for a generic LEON3 device
  • Time limited to 21 days
  • Limited in features, models and simulation time

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Two host platforms are supported: Linux and Windows 10.

Profiling

The TSIM profiling function calculates the amount of execution time spent in and under each subroutine of the simulated program. The profiling is non-intrusive. The Profiling does not have any affect on the execution in terms of simulated time and no changes needs to be done to the instrumented code. Twith both single he profiling information is printed as a list sorted on highest execution time ratio:

tsim> load dhrystone.elf

tsim> profile enable
  profiling enabled, sample period 1000
tsim> run
tsim> profile

  Merged profile for all started CPUs:

  function      ratio(%)
  --------      --------
  __bcc_crt0       99.99
  main             99.79
  Func_2           29.22
  strcmp           25.64
  memcpy           17.09
  Proc_8            8.34
  Func_1            4.77
  Proc_7            4.37
  Proc_6            1.78

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Code coverage monitoring

The TSIM code coverage support will monitor internally emulated memory. Default coverage is to combine the data from all CPUs, but it can be monitored indivually per CPU at the cost of larger memory usage. When coverage is enabled, TSIM registers whether a memory location has been read, written or executed. The coverage information can be displayed on the TSIM console or dumped to a file for batch post processing. When coverage is enabled, the simulation performance is decreased compared running TSIM with coverage disabled.

tsim> coverage enable 
  Switched coverage mode to merged. Resetting coverage data.
 
  coverage enabled:
  0xc0000000 - 0xc0200000  : ROM
  0x00000000 - 0x02000000  : SDRAM

tsim> coverage print strcmp
000040cc : 1  1 11  0  1  1  1 11  0  1  1  1  1  1  1  1
0000410c : 9  1  0  0  1  1  1 11  0  1  1  1  1 19  1  1
0000414c : 1 11  1  1  1  9  1  0  0  1  1 19  1  1  1  1
0000418c : 1  9  1  0  0  0  0  1  1  1  0  0  1  9  1  0
000041cc : 0  0  0  0  0  0  0  0  0  0  0  0  1  1  1  1
0000420c : 1  1  1  1  9  1  0  0  0  0  0  0  0  0  0  0
0000424c : 0  0  0  0  1  1 19  1  1  1  0  0  0  0  0  0
0000428c : 0  0  0  0  0  0  0  0  0  0  4  0  0  0  0  0
000042cc : 0  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
0000430c : 0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
0000434c : 0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
0000438c : 4  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
000043cc : 0  0  0  0  0  0  0  1  1  1  1  1  1  1  1  1
0000440c : 1 11  1  1  1 11  1  1  1  1 11  0  1  1  1 11
0000444c : 1  1  1 11  0  1  1  1 19  1  1  1  1  1  1  1
0000448c : 11 1  1  1 19  1  1 11  0  1  1  1  1  1  1  1

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Performance

A collection of performance statistics are automatically calculated and can be displayed with the 'perf' command:

tsim> perf
  Merged performance statistics for all started CPUs:
   Cycles       : 436100835
   Instructions : 334036982
   Overall CPI  :      1.31
   CPU performance (250.0 MHz) :  191.49 MOPS (191.49 MIPS, 0.00 MFLOPS)
   Cache hit rate              :  100.0 % (inst: 100.0, data: 100.0)
   Simulated time              :  1.74 s
   Processor utilisation       : 100.00 %

‍TSIM3 LEON4

‍TSIM3 LEON4 simulates the GR740 LEON4 quad-core chip

TSIM3 LEON4 includes functionality such as:

• High precision quad-core model for GR740 with bus contention and inter-processor effects modelled on a per instruction level
• FPU and MMU emulation
• L2 cache emulation with support for configurable replacement, cache way locking, as well as and protected and uncached regions.
• IOMMU emulation

TSIM emulates the following on-chip peripherals and I/O cores in GR740:

   SpaceWire Router, GRCAN, GPIO, SDRAM CTRL, L2 cache, SPI, Ethernet, GPTIMER, GRIOMMU, UART etc.

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‍TSIM3 LEON3

‍TSIM3 LEON3 simulates the GR712RC LEON3FT dual-core chip, GR716A LEON3FT, GR716B, UT700, UT699E, UT699 and a generic configurable LEON3.

TSIM3 LEON3 includes functionality such as:

• Emulation of LEON3 processors in general and tailored emulation of specific chips
• High precision multi-core model for GR712RC, and generic LEON3 systems, with bus contention and inter-processor effects modelled on a per instruction level
• FPU and MMU emulation

To simplify emulation of LEON3 devices, TSIM emulates on-chip peripherals and I/O cores in the following devices:

• GR712RC: SpaceWire, CAN_OC, GPIO, FTMCTRL, SPI, Ethernet, GPTIMER, GRTIMER, UART etc.
• GR716A: SpaceWire, GRCAN, GPIO, FTMCTRL, Boot ROM, SPI, SPIM, GPTIMER, UART, DAC etc.
• GR716B: SpaceWire Router, GRCANFD, GPIO, FTMCTRL, Boot ROM, SPI, SPIM, GPTIMER, UART, DAC etc.
• UT700: SpaceWire, PCI, Ethernet, CAN_OC, GPIO, SPI etc.
• UT699/E: SpaceWire, PCI, Ethernet, CAN_OC, GPIO etc.

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‍TSIM3 GR716

‍TSIM3 GR716 simulates the GR716A and GR716B LEON3FT microcontrollers. GR716A and GR716B simulation is possible using a TSIM3-LEON3 license or a dedicated TSIM3-GR716 license at a reduced price.

TSIM GR716 includes functionality such as:

• Emulation of the LEON3 in the GR716A and GR716B microcontrollers
• FPU emulation
• Emulation of GR716A on-chip peripherals and I/O cores such as:  SpaceWire, CAN, GPIO, FTMCTRL, Boot ROM, SPI, SPIM, GPTIMER, UART, DAC etc.
• Emulation of GR716B on-chip peripherals and I/O cores such as: SpaceWire Router, CANFD, GPIO, FTMCTRL, Boot ROM, SPI, SPIM, GPTIMER, UART, DAC, etc

Additional GR716A features include:

• Ability to boot from SPIM, SRAM and PROM
• Atomic access support for all APB registers and local data RAM (AND, OR, XOR, Set&Clear).

Additional GR716B features include:

• Ability to boot from SPIM, SRAM and PROM and use WMEM sections
• Real-Time Accelerators (RTA) supported through user modules, example included.

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‍TSIM3 LEON2

‍TSIM3 LEON2 simulates a generic configurable LEON2 as well as the AT697E chip.

TSIM3 LEON2 includes functionality such as:

• Emulation of LEON2 processors in general and tailored emulation of specific chips
• FPU and MMU emulationTSIM emulates on-chip peripherals and I/O cores in the following devices:
  • AT697E: InSilicon PCI interface (master/target), UARTs, memory controller, timer etc.

Scripting

The TSIM3 Simulator and the GRMON3 debugger share a powerful scripting framework based on Tcl. Tcl scripts can adapt to minor differences in the respective Tcl environments so that the same script can be used in both TSIM3 and GRMON3. This enables users to easily transition from the simulation environment to real hardware validation, considerably reducing development time and improving overall productivity.

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LEON/NOEL C/C++ IDE

We provide a quick-start guide on how to set up the Eclipse framework or Microsoft Visual Code to be used for the development of LEON/NOEL-V applications, together with a GCC tool-chain. See the dedicated webpage.

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