NOEL3
Status:
Development
The NOEL3 is a configurable RISC-V processor IP core, described in VHDL. The architecture is designed to utilize a small area footprint and to maintain execution predictability.
Overview
This page describes a running development and no guarantees can be given concerning future product availability. All information on this page is subject to change without notice. Please click this link to sign up to receive notifications about product and documentation updates.
Architecture
Key Tech Spec
Target technology support
Evaluation boards
Ordering information
Development Kit
Licensing
Software
Tools
Block diagram
Supported Hardware
Configuration
Reference Design
Other resources
Detailed features
- 32-bit RISC-V processor – with configurable extensions
- RV32I: integer essential instructions
- M: integer multiplication and division
- A: atomic instructions for concurrency
- F: single-precision floating-point arithmetic
- C: compressed instructions to reduce code size
- B: bit manipulation instructions
- Zfh: half-precision floating-point operations.
- Zfa: additional floating-point instructions
- Debug module
- Deterministic execution time guaranteed by barrel processor architecture
- Configurable number of hardware execution threads (2 to 7)
- One thread is always reserved for SoC operations
- Utilizes tightly coupled memories instead of caches for predictable memory access
- RISC-V PLIC interrupt controller
- Support of AMBA AHB and APB bus for external memory and peripherals
- Companion IP cores for bus fabrics, peripherals, networking and security (GRLIB IP Library)
Downloads
File
Category
Revision
Date
Access
Excel sheet for SoC area estimation
Data sheet and user's manual
2024.4
2024-12-23
Free download
Password/
Contact us
GRLIB Configuration and Development Guide
Data sheet and user's manual
2024.4
2024-12-23
Free download
Password/
Contact us
Frequently asked questions
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