Status:
Available
The FTMCTRL can handle four types of devices: PROM, asynchronous static ram (SRAM), synchronous dynamic ram (SDRAM) and memory mapped I/O devices (I/O). The PROM, SRAM and SDRAM areas can be EDAC-protected using a (39, 7) BCH code
The FTMCTRL can handle four types of devices: PROM, asynchronous static ram (SRAM), synchronous dynamic ram (SDRAM) and memory mapped I/O devices (I/O).
The FTMCTRL is pure RTL. It is fully technology agnostic and can can be implemented in any ASIC or FPGA technology.
For specific information related to Xilinx, Microchip, and Lattice FPGAs, please refer to our dedicated web pages:
Estimation of the resource utilization can be found here: Excel sheet for SoC area estimation
The IP can be obtained under commercial licensing conditions, enabling proprietary designs. Contact sales@gaisler.com for licensing information.
A reduced version of the IP Core named MCTRL is provided in full source code under the GNU GPL version of the GRLIB IP Library. The differences are that EDAC is not supported and only two PROM chip selects are decoded for the MCTRL.
The core supports 8-/16-/32- and 39-bit wide PROM, IO and SRAM memories/devices. And 32-/39-/48. and 64-bit SDRAM memory. SDRAM can either be on the same memory bus as the other memories or on a separate bus. In the former case only 32-/39- and 48-bit SDRAM is supported, in the latter case 32-/39-/48- and 64-bit SDRAM are all supported. EDAC is supported only for 8-bit and 39-bit memories.
External chip-selects are provided for up to to four PROM banks, one I/O bank, five SRAM banks and two SDRAM banks.
Memory accesses are performed through an AHB slave interface while configuration registers are accessed through an APB interface.
File
Category
Revision
Date
Access
Data sheet and user's manual
2024.2
2024-07-15
Free download
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Application note
1.0
2017-04-21
Free download
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Application note
1.0
2015-11-30
Free download
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Application note
1.0
2018-04-17
Free download
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