LEON4

The LEON4 is interfaced using the AMBA 2.0 AHB bus and supports the IP core plug&play method provided in the GRLIB IP library.  The processor supports the MUL, MAC and DIV instructions and an optional IEEE-754 floating-point unit (FPU) and Memory Management Unit (MMU).

The LEON4 cache system consists of separate I/D multi-set Level-1 (L1) caches with up to 4 ways per cache, and an optional Level-2 (L2) cache for increased performance in data-intensive applications.

The LEON4 pipeline uses 64-bit internal load/store data paths, with an AMBA AHB interface of either 64- or 128-bit. Branch prediction, 1-cycle load latency and a 32x32 multiplier results in a performance of 1.7 DMIPS/MHz, or 2.1 CoreMark/MHz.

The LEON4 processor can be synthesized with common synthesis tools such as Synplify, Synopsys DC and Cadence RC. The core area (pipeline, cache controllers and mul/div units) requires only 30 kgates or 4000 LUT, depending on the configuration. The LEON4 processor can also be synthesized with tools from Mentor, Xilinx or Microsemi.

The LEON4 can be obtained under commercial licensing conditions, enabling proprietary designs and taking advantage of a support agreement. Please see the GRLIB IP Core User's Manual - Processor license overview for the license types.

Contact us if you want to use LEON4 in a commercial product.

Being SPARC V8 conformant, compilers and kernels for SPARC V8 can be used with LEON4 (kernels will need a LEON BSP). To simplify software development, We provide several toolchains and operating systems. Check the software overview webpage for all the details.

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The GRMON monitor interfaces to the LEON4 on-chip debug support unit (DSU), implementing a large range of debug functions as well as a GDB gateway.
Debugging is generally done using the GDB debugger, and a graphical front-end. It is possible to perform source-level symbolic debugging, either on a simulator or using real target hardware.

We provide TSIM-LEON4, a high-performance cycle-accurate LEON4 simulator which seamlessly can be attached to gdb and emulate a LEON4 system.

For multi-processor and/or advanced SOC designs, the GRSIM multi-core simulator is available for early software development.

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The LEON4 processor is fully parametrizable through the use of VHDL generics and does not rely on any  global configuration package. It is thus possible to instantiate several processor cores in the same design with different configurations. The LEON4 template designs can be configured using a graphical tool built. This allows new users to quickly define a suitable custom configuration. The configuration tool not only configures the processor, but also other on-chip peripherals such as memory controllers and network interfaces.

The GRLIB IP library contains LEON4 template designs for several popular FPGA prototyping boards.

Pre-synthesized FPGA programming files are also provided, see LEON-RTG4.