TSIM3 LEON4 simulates the GR740 LEON4 quad-core chip.

TSIM3 LEON4 includes functionality such as:

• High precision quad-core model for GR740 with bus contention and inter-processor effects modelled on a per instruction level
• FPU and MMU emulation
• L2 cache emulation with support for configurable replacement, cache way locking, as well as and protected and uncached regions.
• IOMMU emulation
• Standalone Tcl frontend for both automation and interactive use, with tab completion
• Provided as a library to be included in larger simulator frameworks (TLIB)
• Source level debugging via remote connection from GNU Debugger (GDB) with GDB 8.2 support
• 64-bit time for practically unlimited simulation periods
• Detailed device register information down to individual register fields
• Detailed instruction tracing with instruction results and symbolic information
• Detailed AMBA bus tracing that can be presented combined with instruction tracing
• Memory emulation, including SDRAM, PROM and caches.
• Loadable modules to include user-defined device models
• Non-intrusive execution time profiling
• Non-intrusive code coverage monitoring
• Stack backtrace with symbolic information
• Unlimited number of breakpoints and watchpoints
• Checkpointing capability, to save and restore complete simulator state
• Detailed built-in help for both commands and start options

Future updates:

• AHB-split repsonse modelling

All this while still maintaining functionality and the accuracy profile of TSIM2 allowing efficient SW V&V development. Additional devices and some missing features of simulated devices will be added in the future. Please check this page again for future updates.

Two host platforms are supported: Linux and Windows 10.

• TSIM User's Manual

Usage

TSIM can be run in stand-alone mode, or connected through a network socket to the GNU Debugger (GDB). In stand-alone mode, a variety of debugging commands are available to allow manipulation of memory contents and registers, breakpoint/watchpoint insertion, performance measurements, instruction traces and bus traces. Connected to (supported versions of) GDB, TSIM acts as a remote target and supports GDB debug requests. The communication between GDB and TSIM is performed using the GDB extended-remote protocol. Third-party debuggers supporting this protocol can be used.

The screenshot shows Eclipse connected to TSIM via GDB (click on image for a larger view).

Timing

The simulator time is maintained and incremented according the IU and FPU instruction timing. The parallel execution between the IU and FPU is modelled, as well as stalls due to operand dependencies. Instruction timing has been modelled after the real devices. Integer instructions have a higher accuracy than floating-point instructions due to the somewhat unpredictable operand-dependent timing of the FPU. Typical usage patterns have higher accuracy than atypical ones. The simulator time is maintained using 64-bit values providing virtually unlimited simulation time.

Device emulation

TSIM emulates the following on-chip peripherals and I/O cores in GR740:

• SpaceWire Router, GRCAN, GPIO, SDRAM CTRL, L2 cache, SPI, Ethernet, GPTIMER, GRIOMMU, UART etc.

AHB and I/O emulation

TSIM has the capability to be extended with user-defined modules. This can be used to add simulation models of AHB and I/O devices as well as models connected to interfaces simulated by TSIM, such as GPIO and SPI. Such modules are loaded by TSIM at run-time. The modules has access to the simulator event queue, interrupts and other internal data structures, allowing for accurate emulation.  Modules are typically written in C, and can use any features of the host operating system. This provides high simulation performance and capability to communicate with any other framework (e.g. such as EUROSIM or SIMSAT).

Profiling

The TSIM profiling function calculates the amount of execution time spent in and under each subroutine of the simulated program. The profiling is non-intrusive. The Profiling does not have any affect on the execution in terms of simulated time and no changes needs to be done to the instrumented code. Twith both single he profiling information is printed as a list sorted on highest execution time ratio:

tsim> load dhrystone.elf

...
tsim> profile enable
  profiling enabled, sample period 1000
tsim> run
...
tsim> profile

  Merged profile for all started CPUs:

  function      ratio(%)
  --------      --------
  __bcc_crt0       99.99
  main             99.79
  Func_2           29.22
  strcmp           25.64
  memcpy           17.09
  Proc_8            8.34
  Func_1            4.77
  Proc_7            4.37
  Proc_6            1.78
tsim>

Code coverage monitoring

The TSIM code coverage support will monitor internally emulated memory. Default coverage is to combine the data from all CPUs, but it can be monitored indivually per CPU at the cost of larger memory usage. When coverage is enabled, TSIM registers whether a memory location has been read, written or executed. The coverage information can be displayed on the TSIM console or dumped to a file for batch post processing. When coverage is enabled, the simulation performance is decreased compared running TSIM with coverage disabled.

tsim> coverage enable 
  Switched coverage mode to merged. Resetting coverage data.
 
  coverage enabled:
  0xc0000000 - 0xc0200000  : ROM
  0x00000000 - 0x02000000  : SDRAM

tsim> coverage print strcmp
000040cc : 1  1 11  0  1  1  1 11  0  1  1  1  1  1  1  1
0000410c : 9  1  0  0  1  1  1 11  0  1  1  1  1 19  1  1
0000414c : 1 11  1  1  1  9  1  0  0  1  1 19  1  1  1  1
0000418c : 1  9  1  0  0  0  0  1  1  1  0  0  1  9  1  0
000041cc : 0  0  0  0  0  0  0  0  0  0  0  0  1  1  1  1
0000420c : 1  1  1  1  9  1  0  0  0  0  0  0  0  0  0  0
0000424c : 0  0  0  0  1  1 19  1  1  1  0  0  0  0  0  0
0000428c : 0  0  0  0  0  0  0  0  0  0  4  0  0  0  0  0
000042cc : 0  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
0000430c : 0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
0000434c : 0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
0000438c : 4  0  4  0  0  0  0  0  0  0  0  0  0  0  0  0
000043cc : 0  0  0  0  0  0  0  1  1  1  1  1  1  1  1  1
0000440c : 1 11  1  1  1 11  1  1  1  1 11  0  1  1  1 11
0000444c : 1  1  1 11  0  1  1  1 19  1  1  1  1  1  1  1
0000448c : 11 1  1  1 19  1  1 11  0  1  1  1  1  1  1  1