Exploring Register File and Memory Organization in ASIP Synthesis
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Written by Sandi Habinc |
11486 |
Comparison of the Performance of Microprocessors for Space-based Navigation Applications
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12228 |
Successful Use of an Open Source Processor in a Commercial ASIC
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11259 |
Liquid Architecture
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Written by Administrator |
11180 |
Architecture, Memory and Interface Technology Integration of an Industrial/Academic Configurable SoC
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Written by Administrator |
11913 |
Embedded 32-Bit RISC IP Cores and OPEX JavaBytecode Folding
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Written by Administrator |
11617 |
Mixed Static/Dynamic Profiling for Dictionary Based Code Compression
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Written by Administrator |
10662 |
An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined
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Written by Administrator |
10569 |
Hardware/Software Co-Training
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Written by Administrator |
12161 |
Reconfigurable Hardware in Wearable Computing Nodes
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Written by Administrator |
11277 |
Development cost and size estimation starting from high-level specifications
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Written by Administrator |
12567 |
Design Flow for HW / SW Acceleration Transparency in the ThumbPod Secure Embedded System
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Written by Administrator |
14325 |
Low power error resilient encoding for on-chip data buses
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Written by Administrator |
10926 |
Analysis of SEU effects in a pipelined processor
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Written by Administrator |
12919 |
Hardware/Software Co-testing of Embedded Memories in Complex SOCs
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Written by Administrator |
11468 |
Safety-Critical Architectures for Automotive Applications
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Written by Administrator |
11775 |
A Pipelined SoPC Architecture for 2.5 Gbps Network Processing
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Written by Administrator |
11738 |
Experiences Designing a System-on-a-Chip for Small Satellite Data Processing and Control
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Written by Administrator |
12013 |