DDR2 / DDR3

On the memory side, the IP presents a DFI interface for connection to an on-chip physical layer (PHY) that manages the low-level timing and data recovery and then provides the I/O buffers. Towards the system-on-chip, it presents the memory through an AMBA AHB slave interface.

FTADDR can be synthesized with common commercial synthesis tools. The IP model is highly configurable and portable between different implementation technologies, for both FPGA and ASIC. For FPGA, specific imlementations are available for Xilinx Ultrascale and Altera UniPhy technologies.

The IP core is available as a separate package or as an addition to commercial versions of the GRLIB VHDL library.

Contact sales@gaisler.com for licensing information.