DDR2 / DDR3
Status:
Available
FTADDR is a memory controller for DDR2 and DDR3 SDRAM memory devices. It uses a strong error correction code to achieve exceptional fault tolerance.
Overview
FTADDR is a memory controller for DDR2 and DDR3 SDRAM memory devices. It uses a strong error correction code to achieve exceptional fault tolerance.
Architecture
Key Tech Spec
Target technology support
Evaluation boards
Ordering information
Development Kit
Licensing
Software
Tools
Block diagram
Supported Hardware
Configuration
Reference Design
Other resources
Detailed features
- Configurable to have multiple AHB ports with concurrent accesses to different memory banks
- 96-, 64- or 32-bits interface towards SDRAM
- Memory devices of width x8 or x4
- Support for several PHYs
- Generic DFI
- Altera UniPhy (64 bits)
- Xilinx Ultrascale (64 or 64+32)
- Strong error correction code to achieve double device correction capability:
- Deliver correct data despite one full device failure and random SEU-induced errors on the other devices.
- Up to 8 parallel banks (chip selects)
- Can operate autonomously (designed to support also processor-less configurations)
Downloads
File
Category
Revision
Date
Access
Excel sheet for SoC area estimation
Data sheet and user's manual
2024.2
2024-07-15
Free download
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Frequently asked questions
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