Architecture, Memory and Interface Technology Integration of an Industrial/Academic Configurable SoC

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Jürgen Becker, Universitaet Karlsruhe (TH); Martin Vorbach, PACT XPP Technologies AG.

This paper describes the actual status and results of a dynamically Configurable System-on-Chip (CSoC) integration, consisting of a SPARC-compatible LEON processor-core, a commercial coarse-grain XPP-array of suitable size from PACT XPP Technologies AG, and application-tailored global/local memory topology with efficient Amba-based communication interfaces. The given adaptive architecture is synthesized within an industrial/academic SoC project onto 0.18 and 0.13 mm UMC CMOS technologies at Univer-sitaet Karlsruhe (TH). Due to exponential increasing CMOS mask costs, essential aspects for the industry are now adap-tivity of SoCs, which can be realized by integrating recon-figurable re-usable hardware parts on different granularities into Configurable Systems-on-Chip (CSoCs).