Josh Pfrimmer and Kin F. Li, Dept. of Electrical and Computer Engineering, University of Victoria,Victoria, BC, Canada, firstname.lastname@example.org, email@example.com
An industry of IP reuse has developed and is maturing in order to relieve the pressure of escalating design complexity in diminished development time. Electronic system engineers are offered ready-made or customizable functional cores which may be added to designs. This paper will survey and discuss a subset of currently available microprocessor cores, focussing on 32-bit RISC processors. It will introduce a bytecode folding algorithm and a project to implement a combination of that algorithm and a RISC core to create a processor capable of executing both RISC and Java instructions natively. Conclusions will be drawn about which of the surveyed cores is most suitable for this project.