This report further expands the 'logic replication and voting in combinatorial and sequential logic', mentioned in the previous document. In particular implementing redundancy in combinatorial logic is a challenge, since commercial synthesis tools aim to remove any logic redundancy. A VHDL coding method is developed, which reliably allows to infer configurable levels of redundancy in registers and combinatorial logic. Code examples are given as well as synthesis and layout results. Author: Sandi Habinc.