The GR712RC is a dual-core LEON3FT SPARC V8 processor, with advanced interface protocols, designed for high-reliability aerospace applications. The GR712RC is fabricated at Tower Semiconductors Ltd., using standard 180 nm CMOS technology. It employs our radiation-hard-by-design methods and the RadSafeTM technology from Ramon Space, enabling superior radiation hardness and excellent low-power performance.
The GR712RC provides a rich variation of communications interfaces to allow different systems to be implemented using the same device type, thereby simplifying parts procurement. It also brings cost reductions to software development since the core functionality can be reused from application to application, only changing the drivers for the interfaces.
The GR712RC architecture is centered around the AMBA Advanced High-speed Bus (AHB), to which the two LEON3-FT processors and other high-bandwidth units are connected. Low-bandwidth units are connected to the AMBA Advanced Peripheral Bus (APB) which is accessed through an AHB to APB bridge.
The LEON3FT processors provide hardware support for cache coherency, processor enumeration and interrupt steering. Each processor core includes a SPARC Reference Memory Management Unit (SRMMU) and an IEEE-754 compliant double-precision FPU for floating-point operations. It can be utilized in symmetric or asymmetric multiprocessing mode
Packaging, quality and lead time
The GR712RC can be delivered in three quality levels: flight, engineering and prototype. It is provided in a 240-pin, 0.5 mm pitch high-reliability ceramic quad flat package (CQFP-240). Prototype devices and the GR712RC development board are available for immediate delivery. GR712RC is not subject to U.S. ITAR regulation.
For prices and additional lead times, contact email@example.com
GR712RC On Board Computer Reference design
Compressed folders with all the design files are available for download:
- Please check the disclaimer file before downloading the package.
The two LEON3FT processor cores in the GR712RC can be clocked up to 100 MHz (depending on external device choices) over the full military temperature range. This provides up to 200 MIPS and 200 MFLOPS peak performance.
Development board, tools and compilers
We provide the GR712RC development board for GR712RC prototyping and software development, together with development tools such as the TSIM instruction simulator and the GRMON software debugger, and various compilers and operating systems.
We also provide test equipment for the GR712RC CCSDS / ECSS telemetry and telecommand and SpaceWire functions.
(performance figures obsolete)
- Core1553BRM Handbook (contact firstname.lastname@example.org)
- Application note: Handling denormalized numbers with the GRFPU
- Technical note: Examples of Core Supply Power Consumption of the GR712RC, Excel spreadsheet
- Technical note: GR712RC memory production test coverage and usage constraints