DDR2 & DDR3 Memory Controller


FTADDR is a memory controller for DDR2 and DDR3 SDRAM memory devices. It uses a strong error correction code to achieve exceptional fault tolerance.

On the memory side, it presents a DFI interface for connection to an on-chip physical layer (PHY) that manages the low-level timing and data recovery and then provides the I/O buffers. Towards the system-on-chip, it presents the memory through an AMBA AHB slave interface.

  • Configurable to have multiple AHB ports with concurrent accesses to different memory banks
  • 96-, 64- or 32-bits interface towards SDRAM
    • Memory devices of width x8 or x4
  • Support for several PHYs:
    • Generic DFI
    • Altera UniPhy (64 bits)
    • Xilinx Ultrascale (64 or 64+32)
  • Strong error correction code to achieve double device correction capability:
    • Deliver correct data despite one full device failure and random SEU-induced errors on the other devices.
  • Up to 8 parallel banks (chip selects)
  • Can operate autonomously:
    • Designed to support also processor-less configurations
     FTADDR can be synthesized with common commercial synthesis tools.
     The IP model is highly configurable and portable between different
     implementation technologies, for both FPGA and ASIC. For ASIC
     implementations, a DFI compliant PHY and SSTL IO buffers are also

FTADDR is available as a separate package or as an addition to commercial versions of the GRLIB VHDL library. Contact This email address is being protected from spambots. You need JavaScript enabled to view it. for licensing information.
Example designs for Xilinx and Altera FPGA evaluation boards are readily available.


Document File
FTADDR IP User's Manual GRLIB IP Core User's Manual,  see FTADDR