The LEON4 is a synthesizable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable, and particularly suitable for system-on-chip (SOC) designs.

The LEON4 processor can be enhanced with fault-tolerance features against SEU errors.

The processor can be efficiently implemented on FPGA and ASIC technologies and uses standard synchronous memory cells for cache and register file.

Architecture

The LEON4 is interfaced using the AMBA 2.0 AHB bus and supports the IP core plug&play method provided in the GRLIB IP library.  The processor supports the MUL, MAC and DIV instructions and an optional IEEE-754 floating-point unit (FPU) and Memory Management Unit (MMU).

The LEON4 cache system consists of separate I/D multi-set Level-1 (L1) caches with up to 4 ways per cache, and an optional Level-2 (L2) cache for increased performance in data-intensive applications.

The LEON4 pipeline uses 64-bit internal load/store data paths, with an AMBA AHB interface of either 64- or 128-bit. Branch prediction, 1-cycle load latency and a 32x32 multiplier results in a performance of 1.7 DMIPS/MHz, or 2.1 CoreMark/MHz.

Availability and licensing

The LEON4 can be obtained under commercial licensing conditions, enabling proprietary designs and taking advantage of a support agreement. Please see the GRLIB IP Core User's Manual - Processor license overview for the license types.

Contact us if you want to use LEON4 in a commercial product.

Synthesis

The LEON4 processor can be synthesized with common synthesis tools such as Synplify, Synopsys DC and Cadence RC. The core area (pipeline, cache controllers and mul/div units) requires only 30 kgates or 4000 LUT, depending on the configuration. The LEON4 processor can also be synthesized with tools from Mentor, Xilinx or Microsemi.

Detailed Feature Set

• SPARC V8 instruction set with V8e extensions
• Advanced 7-stage pipeline, with branch prediction
• 64-bit single-clock load/store operation
• 64-bit 4-port register file
• Hardware multiply, divide and MAC units
• High-performance, fully pipelined IEEE-754 FPU
• Separate instruction and data L1 cache (Harvard architecture) with snooping
  • Configurable caches L1: 1 - 4 ways, 1 - 256 kbytes/way. Random, LRR or LRU replacement
• Configurable L2 cache: 256-bit internal, 1-4 ways, 16 Kbyte - 8 Mbyte
• SPARC Reference MMU (SRMMU) with configurable TLB

• SPARC Reference MMU (SRMMU) with configurable TLB
• AMBA 2.0 AHB bus interface, 64- or 128-bit wide
• Advanced on-chip debug support with instruction and data trace buffer, and performance counter
• Symmetric Multi-processor support (SMP)
• Power-down mode and clock gating
• Robust and fully synchronous single-edge clock design
• Up to 150 MHz in FPGA and 1500 MHz on 32 nm ASIC technologies
• Extensively configurable
• Large range of software tools: compilers, kernels, simulators and debug monitors
• High performance: 1.7 DMIPS/MHz, 2.1 CoreMark/MHz, 0.35 (estimated) SPECint2000/MHz

Software Ecosystem

Being SPARC V8 conformant, compilers and kernels for SPARC V8 can be used with LEON4 (kernels will need a LEON BSP). To simplify software development, We provide several toolchains and operating systems.

Check the software overview webpage for all the details.

Debugging is generally done using the GDB debugger, and a graphical front-end such as DDD or Eclipse. It is possible to perform source-level symbolic debugging, either on a simulator or using real target hardware.

We provide TSIM, a high-performance LEON4 simulator which seamlessly can be attached to gdb and emulate a LEON4 system at more than 30 MIPS. The GRMON monitor interfaces to the LEON4 on-chip debug support unit (DSU), implementing a large range of debug functions as well as a GDB gateway. For multi-processor and/or advanced SOC designs, the GRSIM multi-core simulator is available for early software development.

Documentation

- GRLIB IP Core User's Manual,  see LEON4