We have proudly announced from the RISC-V Summit that its new NOEL-V processor model developed out of its design center, Gaisler, is in use by daiteq’s European Space Agency (ESA) research activity, “Evaluation and Instruction Set Extension of a RISC-V Soft Core for Space.”
The NOEL-V processor IP core is available under a dual licensing scheme, both as a commercial license and in a free open source version, as part of Gaisler’s GRLIB IP core library. To enable research and commercialization of third-party extensions, Gaisler also provides a free license for select ESA technology research activities. daiteq is the first company to access the commercial variant of NOEL-V under this scheme.
“We appreciate Gaisler’s approach that enables us to evaluate arithmetic extensions with the NOEL-V processor,” said Martin Daněk, Managing Director of daiteq. ”We expect that this will increase the potential of our work for future ESA missions and other areas that may benefit from using custom-precision arithmetic in NOEL-V.”
daiteq’s work is based on instruction set extensions that it has created for efficient Global Navigation Satellite System (GNSS) processing in the LEON2-FT processor. This development is supported by ESA within its General Support Technology Programme (GSTP). The work also includes implementation trials and evaluation of the NOEL-V processor IP core targeting NanoXplore BRAVE 65nm FPGAs, based on an existing technology mapping for NanoXplore FPGAs that daiteq has created for LEON2-FT.
“Granting access to commercial licenses and IP for research activities is one of the steps we are taking to enable adoption of RISC-V technology in general and the NOEL-V architecture specifically,” said Sandi Habinc, General Manager, Gaisler. “daiteq’s previous work on extending LEON processors has been interesting and of high quality, and we look forward to seeing the results of the current ESA activity.”
Gaisler is a Strategic Member of RISC-V International, which directs the future development and adoption of the RISC-V Instruction Set Architecture (ISA), an open, free instruction set architecture that enables a new era of processor innovation through open standard collaboration.
