Overview

The FTAHBRAM implements volatile memory that is protected by means of Error Detection And Correction (EDAC). One error can be corrected and two errors can be detected,  using a (32, 7) BCH code or by technology specific protection provided by the target technology block RAMs.

The on-chip memory is accessed via an AMBA AHB slave interface. The memory implements a configurable amount of accessible memory (configured via the kbytes VHDL generic). Registers are accessed via an AMBA APB interface.

Architecture

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Key Tech Spec

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Target technology support

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Evaluation boards

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Ordering information

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Development Kit

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Licensing

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Software

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Tools

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Block diagram

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Supported Hardware

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Configuration

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Reference Design

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Other resources

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Detailed features

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Downloads

File

Category

Revision

Date

Access

GRLIB IP Cores Manual

Data sheet and user's manual

2024.4

2024-12-23

Free download

Password/
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GRLIB User's Manual

Data sheet and user's manual

2024.4

2024-12-23

Free download

Password/
Contact us

Excel sheet for SoC area estimation

Data sheet and user's manual

2024.4

2024-12-23

Free download

Password/
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