SPI Controller

The SPI bus parameters are highly configurable via registers, the core has configurable ord length, bit ordering and clock gap insertion. All SPI modes are supported and also a 3-wire mode where the core uses one bidirectional data line. In slave mode the core synchronizes the incoming clock and can operate in systems where other SPI devices are driven by asynchronous clocks. The core can also be configured to automatically perform periodic transfers of a specified length.

The IP can be implemented in any ASIC or FPGA technology. For specific information related to Xilinx, Microchip, and Lattice FPGAs, please refer to our dedicated web pages:

• Specific support for Lattice FPGAs
• Specific support for Microchip FPGAs
• Specific support for Xilinx FPGAs

Estimation of the resource utilization can be found here:
Excel sheet for SoC area estimation

The IP core is part of the GRLIB IP library, and as such provided in full source code under the GNU GPL License.

Commercial licensing is also possible, contact sales@gaisler.com for more information.

Software drivers are available for RTEMS and Linux.