GR-CPCIS-XCKU

The FPGA development board has the following features:

• AMD/Xilinx Kintex Ultrascale.
• Optional - GR716B Microcontroller
  
  • FPGA configuration memory programming scrubbing
• FPGA interface to DDR3 SDRAM via two SODIMM connectors.
  • 64-bit data bus on first SODIMM. Up to 4GiB.
  • 32-bit data bus on second SODIMM. Up to 2GiB.
• SPI flash for FPGA configuration (512 Mbit)
• The FPGA has also access to two NVM:
  • 512 Mbit SPI
  • 64Mbit Parallel Flash memory (40 bit wide)
• Power, Reset, Clock and Auxiliary circuits.
• LPC 1.8V FMC Mezzanine expansion connector.
• Scrubbing interface for the FPGA configuration memory.
• A 2×10 connector to interface with a GR-ACC-6U_6UART breakout board providing access to 6 UARTS (or 16 GPIOs).

The backplane interfaces of the board are:‍

• 8 x SpaceFibre for full-mesh interconnect using FPGA GTH banks
• 8 x SpaceWire for dual-star interconnect
• Dual-redundant CAN-bus
• SGPIO and I2C connected to FPGA with jumper-configurable pull-ups
• 12V supply from backplane that can be turned off by the external input PS_ON#
• Other utility signals connected to the FPGA

The front-panel interfaces are:‍

• 2xUSB ports for:
  • JTAG access to FPGA and FMC (separate chains)
• 2x RJ45 to FPGA via magnetics and Gbit Ethernet transceivers.
  • RGMII interface to FPGA
• 1x eSATA for SpaceFibre to FPGA via CML redriver.
• 2x MDM9 for SpaceWire via LVDS transceivers/repeaters to FPGA.
• Status LEDs, push-buttons and switches
• 2xSMA or 2xSMB for PPS time distribution to FPGA.
• 6U high, 1 slot wide module for mounting in the controller slot of a 6U rack with a CPCI-S Space Backplane.
• The dimensions of the main PCB are 233.35x160mm (excluding the connector protrusions).

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