GR712RC Dual-Core LEON3FT SPARC V8 Processor


The GR712RC is a dual-core LEON3FT SPARC V8 processor, with advanced interface protocols, designed for high-reliability aerospace applications. The GR712RC is fabricated at Tower Semiconductors Ltd., using standard 180 nm CMOS technology. It employs our radiation-hard-by-design methods and the RadSafeTM technology from Ramon Space, enabling superior radiation hardness and excellent low-power performance.

GR712RC Dual-Core LEON3FT SPARC V8 Processor The GR712RC provides a rich variation of communications interfaces to allow different systems to be implemented using the same device type, thereby simplifying parts procurement. It also brings cost reductions to software development since the core functionality can be reused from application to application, only changing the drivers for the interfaces.


GR712RC block diagram

 The GR712RC architecture is centered around the AMBA Advanced High-speed Bus (AHB), to which the two LEON3-FT processors and other high-bandwidth units are connected. Low-bandwidth units are connected to the AMBA Advanced Peripheral Bus (APB) which is accessed through an AHB to APB bridge.

The LEON3FT processors provide hardware support for cache coherency, processor enumeration and interrupt steering. Each processor core includes a SPARC Reference Memory Management Unit (SRMMU) and an IEEE-754 compliant double-precision FPU for floating-point operations. It can be utilized in symmetric or asymmetric multiprocessing mode

Packaging, quality and lead time

The GR712RC can be delivered in three quality levels: flight, engineering and prototype. It is provided in a 240-pin, 0.5 mm pitch high-reliability ceramic quad flat package (CQFP-240). Prototype devices and the GR712RC development board are available for immediate delivery. GR712RC is not subject to U.S. ITAR regulation.

For prices and additional lead times, contact


GR712RC On Board Computer Reference design

We have developed a reference design for an on board computer based on the GR712RC. The design has been adopted in the JUICE mission and has been used in seven out of the ten JUICE science instruments.
The reference design data package consists of schematics and other design files required for developing an on board computer for flight. The reference design includes:

  • Schematics & EEE Parts lists
  • Assembly Drawings
  • Hardware design description
  • Failure Mode and Effects Analysis
  • Timing Analysis
  • Radiation Analysis report
  • Worst Case Analysis

Compressed folders with all the design files are available for download:

- Please check the disclaimer file before downloading the package.
- Contact for the password
- Download GR712RC OBC Reference Design



Detailed Feature Set

  • Two LEON3FT SPARC V8 compliant 32-bit processors, each with:
    • SPARC reference memory management unit (SRMMU) with 32 TLB entries
    • High-performance double-precision IEEE-754 floating point co-processor (GRFPU)
    • 16 KiB multi-way instruction cache and 16 KiB multi-way data cache
  • Internal on-chip high speed AMBA (AHB) bus
  • Instruction trace and AMBA (AHB) trace buffers for debugging
  • Timer unit with four 32-bit timers including watchdog
  • Secondary timer unit with four 32-bit timers
  • Primary and secondary interrupt controller for 31 interrupts
  • On-chip 192 kByte memory block with EDAC
  • External memory support:
    • Data bus width: 8 bits, or 32 bit data plus 8/16 bits for EDAC checkbits
    • 8 bit BCH EDAC for SRAM and PROM, 16 bit Reed-Solomon EDAC for SDRAM
    • Memory types: SRAM, SDRAM, FLASH PROM / EEPROM and parallel I/O
    • Programmable wait-states:
    • SRAM read/write cycle 2 - 5 clock cycles
    • PROM / EEPROM / NOR-FLASH read cycle 2 - 32 clock periods
  • Debug Support Unit (DSU) accessed via JTAG and SpaceWire RMAP targets
  • Two SpaceWire ports with RMAP targets, maximum 200 Mbps full-duplex data rate
  • Configurable I/O selection matrix, connecting a subset of available I/O units to 67 shared pins:
    • Four SpaceWire ports, maximum 200 Mbps full-duplex data rate
    • Redundant MIL-STD-1553B BRM (BC/RT/BM) interface
    • Two CAN 2.0B bus controllers
    • Six UART ports, with 8-byte FIFO
    • Ethernet MAC with RMII 10/100 Mbps port
    • SPI master serial port
    • I2C master serial port
    • ASCS16 (STR) serial port
    • SLINK 6 MHz serial port
    • CCSDS/ECSS 5-channel Telecommand decoder, 10 Mbps input rate
    • CCSDS/ECSS Telemetry encoder, 50 Mbps output rate
    • 26 input and 38 input/output general purpose ports


The two LEON3FT processor cores in the GR712RC can be clocked up to 100 MHz (depending on external device choices) over the full military temperature range. This provides up to 200 MIPS and 200 MFLOPS peak performance.


Development board, tools and compilers

We provide the GR712RC development board for GR712RC prototyping and software development, together with development tools such as the TSIM instruction simulator and the GRMON software debugger, and various compilers and operating systems.

We also provide test equipment for the GR712RC CCSDS / ECSS telemetry and telecommand and SpaceWire functions.



- GR712RC Data Sheet

- GR712RC User's Manual

- GR712RC Product Brief

- Core1553BRM Handbook (contact

- Technical Note on LEON SRMMU Behaviour

- Application note: Handling denormalized numbers with the GRFPU

- Technical note: Examples of Core Supply Power Consumption of the GR712RC, Excel spreadsheet

- Technical note: GR712RC memory production test coverage and usage constraints