NAND Flash Memory Controller with DMA



NANDFCTRL2 is a VHDL IP core implementing an interface to NAND flash memory devices. The core supports ONFI 4.0 and provides DMA transfers to and from the memory. The core implements a BCH EDAC with capability of correcting 60 errors per chunks of 1024 bytes of data. The actual error correction capability is configured by means of VHDL generics, in conjunction with the configuration of memory support. The EDAC can be combined with a data randomizer, which breaks any repetetive bit patterns, thereby increasing memory endurance. Both the EDAC and the Randomizer can be bypassed during runtime if the user needs to access the memory without them. To support detection and recovery from SEFI, the core provides timeout functions in addtion to the EDAC. The SEFI detection functionality monitors ongoing accesses towards the flash to detect if any access is too long, which could indicate an error in the memory.




NANDFCTRL2 can optionally be implemented without an EDAC and have the functionality implemented in software in order to save hardware resources when targeting smaller devices.

For details about the actual flash memory interface, flash memory architecture and ONFI 4.0 command set please refer to the Open NAND Flash Interface specification, revision 4.0.

The NAND Flash controller has the following features:
  • ONFI 4.0 support
    • All mandatory ONFI 4.0 commands
    • Asynchronous / SDR data interface timing mode 0-5
  • BCH EDAC with up to 60 bits correction capacity per 1024 bytes chunks of data
  • Randomization of memory data
  • Basic timeout based SEFI detection and reporting
  • 8-bit data interface with support for up to 64 targets and 16 channels (16x 8 bits data channels)

NANDFCTRL2 is part of the GRLIB IP Library from April 2022 and can be licensed as a separate add-on. The current version of the core is suitable for FPGA implementations for evaluation and integration purposes. Additional features for the NANDFCTRL2 IP core will become available as part of milestone releases. The table below shows the planned milestones. Please note that the future milestone features and dates are tentative.


Milestone Description Target users Date
Release 1.6 Release 1.6 adds increased performance and prototyping support:
  • Increased performance.
  • Added support for more ONFI commands (optionals).
  • Improved verification coverage.
  • Updated documentation.
  • Added support for  up to 64 targets and 16 channels (16x 8 bits data channels)
Users that want to evaluate NAND flash memories in FPGA platforms. Suitable for inclusion in FPGA prototypes during development of products. 2022-Dec (Available)
Release 2 Release 2 adds synchronous interface and ASIC support:
  • Command support. Additional optional ONFI commands and vendor-specific commands
  • Improved performance and scalability including integrated multi-plane support
  • Synchronous interfaces: NV-DDR, NV-DDR2 and NV-DDR3 targeting technology specific PHY. Note: The controller depends on 3rd party PHY to support NV-DDRx. A PHY is not included in the release.
  • Timing mode 0-5 in NV-DDR
  • Timing mode 0-9 in NV-DDR2 and NV-DDR3
  • Feature to read flash memory soft bits to enable a software LDPC implementation.
  • FT features.
  • ASIC implementation support.
Users that want to include NAND flash memories in products. Suitable for both ASIC and FPGA implementation. 2023-Jun
Future implementations Future implementations are pending customer demands and include:
  • FPGA integration for NV-DDR, NV-DDR2 and NV-DDR3 including PHY for Xilinx Ultrascale.
  • FPGA integration for NV-DDR, NV-DDR2 and NV-DDR3 including PHY for Microsemi Polarfire.
  • Hardware LDPC ECC for supporting MLC and TLC modes.
Users that want to include NAND flash memories in products. Suitable for both ASIC and FPGA implementation. Pending customer demand


Example bitstreams are available for evaluation for the Xilinx Kintex UltraScale FPGA KCU105 Evaluation Kit and the Alpha Data ADA-SDEV-KIT3 board. To get access to evaluation bitstreams, contact This email address is being protected from spambots. You need JavaScript enabled to view it.. Note that the example bitstreams require a mezzanine board with the target NAND flashes. For mezzanine boards, contact the NAND flash supplier. 

The bitstreams have been tested with UT81NDQ512G8T and 69F256G16 from DDC.



 Document  File
 NANDFCTRL2 IP Core User's Manual  nandfctrl2.pdf (December 2022)