NANDFCTRL2 is a VHDL IP core implementing an interface to NAND flash memory devices. The core supports ONFI 4.0 and provides DMA transfers to and from the memory. The core implements a BCH EDAC with capability of correcting 60 errors per chunks of 1024 bytes of data. The actual error correction capability is configured by means of VHDL generics, in conjunction with the configuration of memory support. The EDAC can be combined with a data randomizer, which breaks any repetetive bit patterns, thereby increasing memory endurance. Both the EDAC and the Randomizer can be bypassed during runtime if the user needs to access the memory without them. To support detection and recovery from SEFI, the core provides timeout functions in addtion to the EDAC. The SEFI detection functionality monitors ongoing accesses towards the flash to detect if any access is too long, which could indicate an error in the memory.
NANDFCTRL2 can optionally be implemented without an EDAC and have the functionality implemented in software in order to save hardware resources when targeting smaller devices.
|For details about the actual flash memory interface, flash memory architecture and ONFI 4.0 command set please refer to the Open NAND Flash Interface specification, revision 4.0.|
|The NAND Flash controller has the following features:
NANDFCTRL2 is part of the GRLIB IP Library from April 2022 and can be licensed as a separate add-on. The current version of the core is suitable for FPGA implementations for evaluation and integration purposes. Additional features for the NANDFCTRL2 IP core will become available as part of milestone releases. The table below shows the planned milestones. Please note that the future milestone features and dates are tentative.
|Release 1.5||Release 1.5 adds improved software interface:
||Users that want to evaluate NAND flash memories in FPGA platforms.||2022-Jul|
|Release 2||Release 2 adds synchronous interface and general improvements:
||Users that want to integrate and evaluate NAND flash memories in FPGA platforms. Suitable for inclusion in FPGA prototypes during development of products.||2022-Dec|
|Release 3||Release 3 adds MLC, TLC modes and additional improvements:
||Users that want to include NAND flash memories in products. Suitable for both ASIC and FPGA implementation.||2023-Jun|
The bitstreams have been tested with UT81NDQ512G8T from CAES and 69F256G16 from DDC.
|NANDFCTRL2 IP Core User's Manual||nandfctrl2.pdf (April 2022)|