GRLIB Xilinx

The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SoC) development. The modular SoC designs are built from IP cores with common on-chip bus interfaces and use a coherent method for simulation and synthesis. The library is vendor-independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources. The library includes several processor models, including the fault-tolerant LEON3FT 32-bit SPARC V8 and the NOEL-V RISC-V processor models. Designs based on the GRLIB IP library are highly portable between target technologies. GRLIB contains template designs for several Xilinx FPGA boards (the set of included template designs changes with type of GRLIB distribution). A list of supported boards is available in the GRLIB IP Library User's Manual.

Estimation of the resource utilization  of the different IPs in AMD/Xilinx FPGAs can be found here: Excel sheet for SoC area estimation

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Contact us if you want to evaluate GRLIB IP cores on AMD/XIlinx FPGAs or if you want to use GRLIB in a commercial product.

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