This page provides a brief overview of the software components provided by us for the NOEL-V 32- and 64-bit RISC-V. The software ecosystem for our LEON processor family is described here and its software life cycle. Software are also available through other vendors, our partners and open-source communities:
The software provided by us aims to be available for all our FPGA platforms, devices and custom designs making it possible to select any OS and tool for any processor device when starting a new project. The hardware configuration selected by impose limitation of choice.
The software provided are mainly NOEL-V BSPs, device drivers and compiler toolchains together with the integration into the developer tools / ecosystem. Currently we provide NOEL-V SW packages for:
Currently we do not provide NOEL-V specific boot loading support.
The RISC-V target software needs a Flattened Device Tree (FDT) which describes the hardware system for the OS to find devices and adapt to other system settings. A Device Tree Binary (DTB) is normally loaded into main memory by the boot loader or the GRMON hardware debugger and a pointer to the DTB is given to the OS at boot. The DTB can be built by compiling the Device Tree Source (DTS) specific for the NOEL-V hardware design.
DTS files, describing NOEL-V template designs and FPGA bit-streams, for NOEL-V FPGA demonstration boards are found on their home page, for example the NOEL-V Xilinx KCU105 board, and referenced from the board's the Quick Start Guide.
GRLIB systems classically include AMBA Plug & Play information describing the system buses, I/O registers, interrupts and so on. If the OS/BSP supports reading the AMBA PnP information the DTS may not be needed.
It is recommended to visit the board Quick Start Guide or OS documentation to find specific constrains on the DTB target memory location that may exist.
NOEL-V is supported through the generic RISC-V ISA support and tested using the compilers listed below and provided pre-built for NOEL-V within the prepared SW components:
We provide the GRMON hardware debugger solution for NOEL-V. It can be used to perform board bring-up, application uploading and execution, RISC-V assembly debugging and C/C++ debugging via GDB or Eclipse CDT IDE without any additional hardware adapter required. The Evaluation version is compatible with the prebuilt FPGA bitstreams provided here and for custom GRLIB designs built on the GPL release for free. For commercial GRLIB designs a Professional license for GRMON is required, see ordering.
For a detailed overview of a specific device and environment please consult the SW product's manual and the software overview in the board Quick Start Guide. This section does not cover custom GRLIB SoC designs.
|GRMON download page|
|DTS/DTB files for NOEL-V FPGA demonstration boards|
|VxWorks 7 SR0650 with LLVM/Clang toochain provided by us under commercial license|
|NOEL-V buildroot 2021.02LTS distribution with Linux kernel and OpenSBI (md5)|
|Sample Linux image (SMP, networking, login as root) for NOEL-V RV32IMA and RV64IMA (md5)|
|NOEL-V (RV32GCH) buildroot 2021.02LTS Cross Compilation toolchain (md5)|
|NOEL-V (RV64GCH) buildroot 2021.02LTS Cross Compilation toolchain (md5)|
|NOEL-V RTEMS5 Software Development Environment (md5)|
|Optional RTEMS kernel source (md5)|
|Bare-metal C/C++ toolchain|
|NCC GNU GCC C/C++ bare-metal toolchain (linux64) (md5) 1)|
|NCC GNU GCC C/C++ bare-metal toolchain (mingw64) (md5) 1)|
|NCC bare-metal sources (md5)|
|Zephyr RTOS NOEL-V BSP available on request|
Most of the software packages provided by us are freely available under different open source licenses. The following products require a commercial license, with exceptions listed:
For license inquiries please contact email@example.com for more information.