NOEL-V

The NOEL-V can be implemented as a dual-issue processor, allowing up to two instructions per cycle to be executed in parallel. To support the instruction issue rate of the pipeline, the NOEL-V has advanced branch prediction capabilities. The cache controller of the NOEL-V supports a store buffer FIFO with one cycle per store sustained throughput, and wide AHB slave support to enable fast stores and fast cache refill.

The NOEL-V is interfaced using the AMBA 2.0 AHB bus (but a subsystem with Level-2 cache and AXI4 backend is also available) and supports the IP core plug&play method provided in our IP library (GRLIB). The processor can be efficiently implemented on FPGA and ASIC technologies and uses standard synchronous memory cells for caches and register file.

The NOEL-V processor is inherently portable and can be implemented on any FPGA and ASIC technologies. For specific information related to Xilinx, Microchip, and Lattice FPGAs, please refer to our dedicated web pages:

• Specific support for Lattice FPGAs
• Specific support for Microchip FPGAs
• Specific support for Xilinx FPGAs

Estimation of the resource utilization for the NOEL-V can be found here: Excel sheet for SoC area estimation

We also provide NOEL-V example bitfiles for evaluation purposes. FPGA programming files are available for the following FPGA boards:

• Digilent Arty-A7: NOEL-ARTYA7 example designs
• Microsemi PolarFire Splash Kit: NOEL-PF example designs
• Xilinx KCU105: NOEL-XCKU example designs

NOEL-V is part of the GRLIB IP library. The open-source version of the library is distributed under the GNU GPL license and can be downloaded here. The open source version of the NOEL-V does not include features such as fault-tolerance and high-performance FPU.

The NOEL-V can be obtained under commercial licensing conditions, enabling proprietary designs and taking advantage of a support agreement. Please see the GRLIB IP Core User's Manual - Processor license overview for the license types.

Contact us if you want to use NOEL-V in a commercial product

Please see the GRLIB IP Core User's Manual - Processor license overview for the license types available for the NOEL-V processor.

Please visit the NOEL-V Software overview webpage for all the details.

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All the configurations are available in 32 or 64 bits architecture.

*Several other ratified extensions, such as Zbkx, Zicbom, Zfh, Sscofpmf and Sstc are also implemented. Please see the list of the implemented extensions in the chapter NOELVSYS of the GRLIB IP core User's Manual.

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