Combined PROM/IO/SRAM

The FTSRCTRL uses a common 32-bit memory bus to interface 32-bit PROM, IO and SRAM devices. 8-bit PROM devices are also supported. It also provides EDAC correcting one and detecting two errors for the PROM and SRAM areas using a (39, 7) BCH code.

One chip select is decoded for the IO-area while SRAM and PROM can have up to 8 chip selects.

Memory accesses are performed through an AHB slave interface while configuration registers are accessed through an APB interface.