GRLIB NanoXplore

The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SoC) development. The modular SoC designs are built from IP cores with common on-chip bus interfaces and use a coherent method for simulation and synthesis. The library is vendor-independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources. The library includes several processor models, including the fault-tolerant LEON3FT 32-bit SPARC V8 and the NOEL-V RISC-V processor models. Template designs are available for NanoXplore FPGAs.

Estimation of the resource utilization  of the different IPs in NG-Medium and NG-Ultra FPGAs can be found here: Excel sheet for SoC area estimation

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Contact us if you want to evaluate GRLIB on NanoXplore FPGAs or if you want to use GRLIB in a commercial product.

The library infrastructure provides project generation support for the NanoXplore Impulse software environment.