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I²C Master
Status:
Available
The I²C master core is a simple I²C master that provides a link between the I²C bus and the AMBA APB.
Overview
The I²C-master core is a modified version of the OpenCores I²C-Master where the WISHBONE interface has been replaced with an AMBA APB interface. The core is compatible with Philips I²C standard and supports 7- and 10-bit addressing. Standard-mode (100 kb/s) and Fast-mode (400 kb/s) operation are supported directly.
Architecture
Key Tech Spec
Target technology support
Evaluation boards
Ordering information
Development Kit
Licensing
Software
Tools
Block diagram
Supported Hardware
Configuration
Reference Design
Other resources
Detailed features
- AMBA APB interface
- Supports 7- and 10-bit addressing
- Bus arbitration (multi master operation)
- Software programmable clock frequency
- Clock stretching
Downloads
File
Category
Revision
Date
Access
Excel sheet for SoC area estimation
Data sheet and user's manual
2024.2
2024-07-15
Free download
Password/
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Frequently asked questions
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