L2 Cache

The cache is a unified cache and in a system with LEON or NOEL processors, data may exist in the Level-1 and Level-2 cache, or only in the Level-1 or Level-2 cache. A front-side AHB interface is connected to the processor bus, while a backend AHB/AXI interface is connected to the memory bus. Both front-side and backend buses can be individually configured to 32, 64 or 128 bits data width. The front-side bus and the backend bus must be clocked with the same clock.

The IP can be obtained under commercial licensing conditions, enabling proprietary designs and taking advantage of a support agreement.

Contact sales@gaisler.com for licensing information

The Level-2 cache can be configured as direct-mapped or multi-way with associativity 2, 3 or 4. The replacement policy for a multi-way configuration can be configured as: LRU (least-recently-used), pseudo-random or master-index (where the way to replace is determined by the master index). The way size is configurable between 1 - 512 KiB with a line size of 32/64 bytes.

EDAC (Error Detection and Correction) protection can be enabled to correct single-bit errors and detect double-bit errors.  Additionally, the IP core includes a hardware scrubber that can be configured to either scrub a specific cache line or continuously loop through all cache lines.

AMBA SPLIT support can also be enabled.

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