PCI Bridge

• 2-bit PCI interface
• PCI bus master and target
• AMBA AHB/APB 2.0 back-end interface
• Configurable FIFOs for both master and target operation
• Supports incremental bursts and single accesses
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Bus master capabilities

• Memory read, memory write
• Memory read multiple
• Memory read line
• I/O read, I/O write
• Type 0 and 1 configuration read and write
• Host bridging

Target capabilities

• Type 0 configuration space header
• Configuration read and write
• Parity generation (PAR)
• 2 Memory BARs
• Memory read, memory write
• Memory read multiple
• Memory read line
• Memory write and invalidate

Optional DMA engine add on

Software support for GRPCI hosts in Linux 2.6, RTEMS and VxWorks