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PCI Bridge
Status:
Available
The GRPCI2 IP core provides a 32-bit master/target interface for AMBA AHB-2.0 systems
Overview
The GRPCI2 IP core provides a 32-bit master/target interface for AMBA AHB-2.0 systems. It includes parameterizable FIFOs for both master and target operation, and can optionally be provided with an independent DMA engine.
Architecture
Key Tech Spec
Target technology support
Evaluation boards
Ordering information
Development Kit
Licensing
Software
Tools
Block diagram
Supported Hardware
Configuration
Reference Design
Other resources
Detailed features
- 2-bit PCI interface
- PCI bus master and target
- AMBA AHB/APB 2.0 back-end interface
- Configurable FIFOs for both master and target operation
- Supports incremental bursts and single accesses
Bus master capabilities
- Memory read, memory write
- Memory read multiple
- Memory read line
- I/O read, I/O write
- Type 0 and 1 configuration read and write
- Host bridging
Target capabilities
- Type 0 configuration space header
- Configuration read and write
- Parity generation (PAR)
- 2 Memory BARs
- Memory read, memory write
- Memory read multiple
- Memory read line
- Memory write and invalidate
Optional DMA engine add on
Software support for GRPCI hosts in Linux 2.6, RTEMS and VxWorks
Downloads
File
Category
Revision
Date
Access
Excel sheet for SoC area estimation
Data sheet and user's manual
2024.2
2024-07-15
Free download
Password/
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Frequently asked questions
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