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SPI Memory Controller
Status:
Available
SPIMCTRL maps a memory device connected via the Serial Peripheral Interface (SPI) into AMBA AHB address space. The core is highly configurable and supports most SPI Flash memory devices.
Overview
The memory controller can be configured to support a wide range of SPI protocols, like DSPI and QSPI. By default only reads are memory mapped in AHB space, and writes are handled by manually sending SPI commands through the cores I/O area. For some SPI memory devices however, especially MRAM memories, it is possible to configure the SPI device and the SPIMCTRL to also allow for memory mapped write operations.
Architecture
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Detailed features
Downloads
File
Category
Revision
Date
Access
Data sheet and user's manual
2024.2
2024-07-15
Free download
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