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The SPI2AHB bridge is an SPI slave that provides a link between a SPI bus (that consists of two data signals, one clock signal and one select signal) and AMBA AHB.
The SPI to AHB bridge is an SPI slave that provides a link between a SPI bus (that consists of two data signals, one clock signal and one select signal) and AMBA AHB. On the SPI bus the slave acts as an SPI memory device where accesses to the slave are translated to AMBA accesses. The core can translate SPI accesses to AMBA byte, half-word or word accesses. The access size to use is configurable via the SPI bus.
The core synchronizes the incoming clock and can operate in systems where other SPI devices are driven by asynchronous clocks.
The IP can be implemented in any ASIC or FPGA technology. For specific information related to Xilinx, Microchip, and Lattice FPGAs, please refer to our dedicated web pages:
Estimation of the resource utilization can be found here:
Excel sheet for SoC area estimation
The IP core is part of the GRLIB IP library, and as such provided in full source code under the GNU GPL License.
Commercial licensing is also possible, contact sales@gaisler.com for more information.
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Data sheet and user's manual
2024.2
2024-07-15
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